SBOS831B December   2016  – June 2021 THS4552

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 6.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 6.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 6.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 6.9 Typical Characteristics: 3 V to 5 V Supply Range
  7. 7 Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 7.3 Output Common-Mode Measurements
    4. 7.4 Differential Amplifier Noise Measurements
    5. 7.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 7.6 Simulated Characterization Curves
    7. 7.7 Terminology and Application Assumptions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential Open-Loop Gain and Output Impedance
      2. 8.3.2 Setting Resistor Values Versus Gain
      3. 8.3.3 I/O Headroom Considerations
      4. 8.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 8.4.2 Operation from a Differential Input to a Differential Output
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 8.4.3 Input Overdrive Performance
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noise Analysis
      2. 9.1.2 Factors Influencing Harmonic Distortion
      3. 9.1.3 Driving Capacitive Loads
      4. 9.1.4 Interfacing to High-Performance Precision ADCs
      5. 9.1.5 Operating the Power Shutdown Feature
      6. 9.1.6 Channel-to-Channel Crosstalk
      7. 9.1.7 Channel-to-Channel Mismatch
      8. 9.1.8 Designing Attenuators
      9. 9.1.9 The Effect of Adding a Feedback Capacitor
    2. 9.2 Typical Applications
      1. 9.2.1 An MFB Filter Driving an ADC Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Analysis
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
    3. 11.3 EVM Board
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TINA-TI Simulation Model Features
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-B33F96E8-4870-45CD-90CF-A5BBAA081952-low.gifFigure 5-1 RTW Package24-Pin VQFN With Exposed Thermal PadTop View
GUID-60C61F39-74A0-4431-87BB-95C3254B7647-low.gifFigure 5-2 PW Package16-Pin VSSOPTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
RTW(1) PW
FB1– 23 — O Channel 1, inverting (negative) output feedback
FB2– 5 — O Channel 2, inverting (negative) output feedback
FB1+ 2 — O Channel 1, noninverting (positive) output feedback
FB2+ 8 — O Channel 2, noninverting (positive) output feedback
IN1– 1 3 I Channel 1, inverting (negative) amplifier input
IN2– 7 7 I Channel 2, inverting (negative) amplifier input
IN1+ 24 2 I Channel 1, noninverting (positive) amplifier input
IN2+ 6 6 I Channel 2, noninverting (positive) amplifier input
OUT1– 19 15 O Channel 1, inverting (negative) amplifier output
OUT2– 13 11 O Channel 2, inverting (negative) amplifier output
OUT1+ 18 14 O Channel 1, noninverting (positive) amplifier output
OUT2+ 12 10 O Channel 2, noninverting (positive) amplifier output
PD1 20 1 I Channel 1, power-down.
PD = logic low = power off mode; PD = logic high = normal operation.
PD2 14 5 I Channel 2, power-down.
PD = logic low = power off mode; PD = logic high = normal operation.
VOCM1 17 4 I Channel 1, common-mode voltage input
VOCM2 11 8 I Channel 2, common-mode voltage input
VS1– 21, 22 16 I Channel 1, negative power-supply input
VS2– 15.16 12 I Channel 2, negative power-supply input
VS1+ 3,4 13 I Channel 1, positive power-supply input
VS2+ 9.10 9 I Channel 2, positive power-supply input
(1) Solder the exposed thermal pad (RTW package) to a heat-spreading power or ground plane. This pad is electrically isolated from the die, but must be connected to a power or ground plane and not floated.