SBOS831B December   2016  – June 2021 THS4552

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 6.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 6.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 6.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 6.9 Typical Characteristics: 3 V to 5 V Supply Range
  7. 7 Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 7.3 Output Common-Mode Measurements
    4. 7.4 Differential Amplifier Noise Measurements
    5. 7.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 7.6 Simulated Characterization Curves
    7. 7.7 Terminology and Application Assumptions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential Open-Loop Gain and Output Impedance
      2. 8.3.2 Setting Resistor Values Versus Gain
      3. 8.3.3 I/O Headroom Considerations
      4. 8.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 8.4.2 Operation from a Differential Input to a Differential Output
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 8.4.3 Input Overdrive Performance
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noise Analysis
      2. 9.1.2 Factors Influencing Harmonic Distortion
      3. 9.1.3 Driving Capacitive Loads
      4. 9.1.4 Interfacing to High-Performance Precision ADCs
      5. 9.1.5 Operating the Power Shutdown Feature
      6. 9.1.6 Channel-to-Channel Crosstalk
      7. 9.1.7 Channel-to-Channel Mismatch
      8. 9.1.8 Designing Attenuators
      9. 9.1.9 The Effect of Adding a Feedback Capacitor
    2. 9.2 Typical Applications
      1. 9.2.1 An MFB Filter Driving an ADC Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Analysis
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
    3. 11.3 EVM Board
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TINA-TI Simulation Model Features
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Typical Characteristics: 3 V to 5 V Supply Range

at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50 Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 7-1 for a gain of 1 V/V test circuit

GUID-4A745D59-7A28-4D03-B54C-15265FA5F0B4-low.gif
Simulated with a 1 kΩ differential load and 0.6 pF internal feedback capacitors removed
Figure 6-37 Main Amplifier Differential Open-Loop Gain and Phase vs Frequency
GUID-97F73045-1C03-4CD9-97AB-D177B8957F47-low.gif
Figure 6-39 Input Spot Noise vs Frequency
GUID-93D1428C-605F-4628-92EE-01D5085BB1D3-low.gif
Common-mode input to differential output, simulated with G = 1 V/V
Figure 6-41 CMRR vs Frequency
GUID-D5422E04-E46F-4F1C-B980-35E2971E25A7-low.gif
Figure 6-43 Common-Mode Voltage, Small- and Large-Signal Response (VOCM Pin Driven)
GUID-153917F8-87FA-4536-9706-CFF2D44C72C4-low.gif
The VOCM pin is either driven to mid-supply by low-impedance source or allowed to float and default to mid-supply
Figure 6-45 Output Common-Mode Noise vs Frequency
GUID-EF4807AA-0281-4EF2-97CC-555E07084D24-low.gif
Simulated with single-ended to differential gain of 1, PSRR for negative supply to differential output
Figure 6-47 –PSRR vs VOCM Approaching VS–
GUID-282A28A2-D93A-40A5-8EE5-E57EC3291150-low.gif
Total of 561 PW units trimmed at a 5 V supply
Figure 6-49 Input Offset Voltage (VIO)
GUID-9904C726-70B2-4570-9749-CB92F7B34F09-low.gif
5 V and 3 V delta from 25°C VIO, 52 PW units
Figure 6-51 Input Offset Voltage vs Temperature
GUID-89937E01-02F4-4194-AD84-56B95CAD8095-low.gif
–40°C to +125°C endpoint drift, total of 52 PW units
Figure 6-53 Input Offset Voltage Drift Histogram
GUID-1C01B5F5-7EAE-475C-AB64-B5A0DF257D67-low.gif
Maximum differential output swing, VOCM at mid-supply
Figure 6-55 ±Maximum VOUT vs Differential Load Resistance
GUID-F892AB44-81DE-4CBD-B9D4-4653CF2F30C2-low.gif
VOCM input floating, total of 240 units
Figure 6-57 Common-Mode Output Offset from VS+ / 2 Default Value Histogram
GUID-8A3B6771-1C47-4384-8A32-83DE9FDA9AE5-low.gif
5 MHz, 2 VPP input, G = 1 V/V, see Figure 7-1
Figure 6-59 PD Turn-On Waveform
GUID-55F5F5A2-7268-45AE-AA7A-D06EF1735099-low.gif
Simulated closed-loop differential output impedance
Figure 6-38 Closed-Loop Output Impedance vs Frequency
GUID-E1874950-7BAF-49EE-83EA-CA050BA9E53A-low.gif
Differential mode output to common-mode output, simulated with G = 1 V/V Note: SSOB is equal to a 20 mVPP output balance (OB).
Figure 6-40 Output Balance vs Frequency
GUID-4B801519-7579-4F8D-AC73-BAD380A5BAFD-low.gif
Single-ended to differential gain of 1, PSRR simulated to differential output
Figure 6-42 Power-Supply Rejection Ratio vs Frequency
GUID-950069AE-2977-466E-B201-24D4A43F544B-low.gif
Figure 6-44 Common-Mode Voltage, Small- and Large-Step Response (VOCM Pin Driven)
GUID-6AA06C87-A260-4A86-8D92-F3BBFB585743-low.gif
Average VOCM output offset of 39 units, standard deviation < 2 mV
Figure 6-46 VOCM Offset vs VOCM Setting
GUID-6DD9E0AD-033E-49EE-BDEF-602B9F233913-low.gif
Simulated with single-ended to differential gain of 1, PSRR for positive supply to differential output
Figure 6-48 +PSRR vs VOCM Approaching VS+
GUID-5DEC0E9C-A39A-45CF-BD42-C199EA84D4FD-low.gif
Total of 561 PW units trimmed at a 5 V supply
Figure 6-50 Input Offset Current (IOS)
GUID-8B68F61D-A836-4901-9A0D-47B59764A396-low.gif
5 V and 3 V delta from 25°C IOS, 52 PW units
Figure 6-52 Input Offset Current vs Temperature
GUID-929921D1-3831-4D1E-B219-6848D69F4C0E-low.gif
–40°C to +125°C endpoint drift, total of 52 PW units
Figure 6-54 Input Offset Current Drift Histogram
GUID-6D01B1EE-03AA-496E-9FD2-0D0D9098A5B1-low.gif
Figure 6-56 Supply Current vs PD Voltage
GUID-43CEA6F2-771C-4542-8D0E-98C2CF2F18D3-low.gif
VOCM input driven to mid-supply, total of 240 units
Figure 6-58 Common-Mode Output Offset from Driven VOCM Histogram
GUID-B7ED0CB0-2C8C-4ECB-9465-EE53B15169AC-low.gif
5 MHz, 2 VPP input, G = 1 V/V, see Figure 7-1
Figure 6-60 PD Turn-Off Waveform