SCPS269 September   2017 TIC12400

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7  Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch inputs Settings
        1. 8.3.8.1 Input Current Source/Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable/disable And Interrupt generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check And Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix Polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
      1. 8.6.1  DEVICE_ID register (Offset = 1h) [reset = 20h]
      2. 8.6.2  INT_STAT Register (Offset = 2h) [reset = 1h]
      3. 8.6.3  CRC Register (Offset = 3h) [reset = FFFFh]
      4. 8.6.4  IN_STAT_MISC Register (Offset = 4h) [reset = 0h]
      5. 8.6.5  IN_STAT_COMP Register (Offset = 5h) [reset = 0h]
      6. 8.6.6  IN_STAT_ADC0 Register (Offset = 6h) [reset = 0h]
      7. 8.6.7  IN_STAT_ADC1 Register (Offset = 7h) [reset = 0h]
      8. 8.6.8  IN_STAT_MATRIX0 Register (Offset = 8h) [reset = 0h]
      9. 8.6.9  IN_STAT_MATRIX1 Register (Offset = 9h) [reset = 0h]
      10. 8.6.10 ANA_STAT0 Register (Offset = Ah) [reset = 0h]
      11. 8.6.11 ANA_STAT1 Register (Offset = Bh) [reset = 0h]
      12. 8.6.12 ANA_STAT2 Register (Offset = Ch) [reset = 0h]
      13. 8.6.13 ANA_STAT3 Register (Offset = Dh) [reset = 0h]
      14. 8.6.14 ANA_STAT4 Register (Offset = Eh) [reset = 0h]
      15. 8.6.15 ANA_STAT5 Register (Offset = Fh) [reset = 0h]
      16. 8.6.16 ANA_STAT6 Register (Offset = 10h) [reset = 0h]
      17. 8.6.17 ANA_STAT7 Register (Offset = 11h) [reset = 0h]
      18. 8.6.18 ANA_STAT8 Register (Offset = 12h) [reset = 0h]
      19. 8.6.19 ANA_STAT9 Register (Offset = 13h) [reset = 0h]
      20. 8.6.20 ANA_STAT10 Register (Offset = 14h) [reset = 0h]
      21. 8.6.21 ANA_STAT11 Register (Offset = 15h) [reset = 0h]
      22. 8.6.22 ANA_STAT12 Register (Offset = 16h) [reset = 0h]
      23. 8.6.23 CONFIG Register (Offset = 1Ah) [reset = 0h]
      24. 8.6.24 IN_EN Register (Offset = 1Bh) [reset = 0h]
      25. 8.6.25 CS_SELECT Register (Offset = 1Ch) [reset = 0h]
      26. 8.6.26 WC_CFG0 Register (Offset = 1Dh) [reset = 0h]
      27. 8.6.27 WC_CFG1 Register (Offset = 1Eh) [reset = 0h]
      28. 8.6.28 CCP_CFG0 Register (Offset = 1Fh) [reset = 0h]
      29. 8.6.29 CCP_CFG1 Register (Offset = 20h) [reset = 0h]
      30. 8.6.30 THRES_COMP Register (Offset = 21h) [reset = 0h]
      31. 8.6.31 INT_EN_COMP1 Register (Offset = 22h) [reset = 0h]
      32. 8.6.32 INT_EN_COMP2 Register (Offset = 23h) [reset = 0h]
      33. 8.6.33 INT_EN_CFG0 Register (Offset = 24h) [reset = 0h]
      34. 8.6.34 INT_EN_CFG1 Register (Offset = 25h) [reset = 0h]
      35. 8.6.35 INT_EN_CFG2 Register (Offset = 26h) [reset = 0h]
      36. 8.6.36 INT_EN_CFG3 Register (Offset = 27h) [reset = 0h]
      37. 8.6.37 INT_EN_CFG4 Register (Offset = 28h) [reset = 0h]
      38. 8.6.38 THRES_CFG0 Register (Offset = 29h) [reset = 0h]
      39. 8.6.39 THRES_CFG1 Register (Offset = 2Ah) [reset = 0h]
      40. 8.6.40 THRES_CFG2 Register (Offset = 2Bh) [reset = 0h]
      41. 8.6.41 THRES_CFG3 Register (Offset = 2Ch) [reset = X]
      42. 8.6.42 THRES_CFG4 Register (Offset = 2Dh) [reset = X]
      43. 8.6.43 THRESMAP_CFG0 Register (Offset = 2Eh) [reset = 0h]
      44. 8.6.44 THRESMAP_CFG1 Register (Offset = 2Fh) [reset = 0h]
      45. 8.6.45 THRESMAP_CFG2 Register (Offset = 30h) [reset = 0h]
      46. 8.6.46 Matrix Register (Offset = 31h) [reset = 0h]
      47. 8.6.47 Mode Register (Offset = 32h) [reset = 0h]
    7. 8.7 Programming Guidelines
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Digital IO Switches and Analog Voltage Monitoring
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DCP Package
38-Pin TSSOP
Top View
TIC12400 pinout-scps260.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 IN13 I/O Ground switch monitoring input with current source
2 IN14 I/O Ground switch monitoring input with current source
3 IN15 I/O Ground switch monitoring input with current source
4 IN16 I/O Ground switch monitoring input with current source
5 IN17 I/O Ground switch monitoring input with current source
6 IN18 I/O Ground switch monitoring input with current source
7 IN19 I/O Ground switch monitoring input with current source
8 IN20 I/O Ground switch monitoring input with current source
9 AGND P Ground for analog circuitry
10 IN21 I/O Ground switch monitoring input with current source
11 IN22 I/O Ground switch monitoring input with current source
12 IN23 I/O Ground switch monitoring input with current source
13 IN0 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
14 IN1 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
15 CS I Active-low input. Chip select from the master for the SPI Interface.
16 SCLK I Serial clock output from the master for the SPI Interface
17 SI I Serial data input for the SPI Interface.
18 SO O Serial data output for the SPI Interface
19 VDD P 3.3 V to 5.0 V logic supply for the SPI communication. The SPI I/Os are not fail-safe protected: VDD needs to be present during any SPI traffic to avoid excessive leakage currents and corrupted SPI I/O logic levels.
20 CAP_A I/O External capacitor connection for the analog LDO. Use capacitance value of 100nF.
21 RESET I Keep RESET low for normal operation and drive RESET high and release it to perform a hardware reset of the device. The RESET pin is connected to ground via a 1MΩ pull-down resistor. If not used, the RESET pin shall be grounded to avoid any accidental device reset due to coupled noise onto this pin.
22 CAP_Pre I/O External capacitor connection for the pre-regulator. Use capacitance value of 1μF.
23 CAP_D I/O External capacitor connection for the digital LDO. Use capacitance value of 100nF.
24 INT O Open drain output. Pulled low (internally) upon change of state on the input or occurrence of a special event.
25 IN2 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
26 IN3 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
27 IN4 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
28 DGND P Ground for digital circuitry
29 IN5 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
30 IN6 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
31 IN7 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
32 IN8 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
33 IN9 I/O Ground/VSUPPLY switch monitoring input with configurable current sink or source.
34 IN10 I/O Ground switch monitoring input with current source
35 IN11 I/O Ground switch monitoring input with current source
36 IN12 I/O Ground switch monitoring input with current source
37 VS P Power supply input pin.
38 VS P Power supply input pin.
--- EP P Exposed Pad. The exposed pad is not electrically connected to AGND or DGND. Connect EP to the board ground to achieve rated thermal and ESD performance.
(1) I = input, O = output, I/O = input and output, P = power.