SLOS080T September   1978  – December 2021 TL071 , TL071A , TL071B , TL071H , TL072 , TL072A , TL072B , TL072H , TL072M , TL074 , TL074A , TL074B , TL074H , TL074M

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings: TL07xH
    2. 6.2  Absolute Maximum Ratings: All Devices Except TL07xH
    3. 6.3  ESD Ratings: TL07xH
    4. 6.4  ESD Ratings: All Devices Except TL07xH
    5. 6.5  Recommended Operating Conditions: TL07xH
    6. 6.6  Recommended Operating Conditions: All Devices Except TL07xH
    7. 6.7  Thermal Information for Single Channel: TL071H
    8. 6.8  Thermal Information: TL071x
    9. 6.9  Thermal Information for Dual Channel: TL072H
    10. 6.10 Thermal Information: TL072x
    11. 6.11 Thermal Information: TL072x (cont.)
    12. 6.12 Thermal Information for Quad Channel: TL074H
    13. 6.13 Thermal Information: TL074x
    14. 6.14 Thermal Information: TL074x (cont).
    15. 6.15 Thermal Information: TL074x (cont).
    16. 6.16 Thermal Information
    17. 6.17 Electrical Characteristics: TL07xH
    18. 6.18 Electrical Characteristics: TL071C, TL072C, TL074C
    19. 6.19 Electrical Characteristics: TL071AC, TL072AC, TL074AC
    20. 6.20 Electrical Characteristics: TL071BC, TL072BC, TL074BC
    21. 6.21 Electrical Characteristics: TL071I, TL072I, TL074I
    22. 6.22 Electrical Characteristics: TL071M, TL072M
    23. 6.23 Electrical Characteristics: TL074M
    24. 6.24 Switching Characteristics: TL07xM
    25. 6.25 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI
    26. 6.26 Typical Characteristics: TL07xH
    27. 6.27 Typical Characteristics: All Devices Except TL07xH
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Total Harmonic Distortion
      2. 8.3.2 Slew Rate
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Unity Gain Buffer
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
    4. 9.4 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • PS|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics: TL07xH

For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±1 ±4 mV
TA = –40°C to 125°C ±5
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±2 µV/℃
PSRR Input offset voltage versus power supply VS = 5 V to 40 V, VCM = VS / 2 TA = –40°C to 125°C ±1 ±10 μV/V
Channel separation f = 0 Hz 10 µV/V
INPUT BIAS CURRENT
IB Input bias current  ±1 ±120 pA
DCK and DBV packages ±1 ±300 pA
TA = –40°C to 125°C (1) ±5 nA
IOS Input offset current  ±0.5 ±120 pA
DCK and DBV packages ±0.5 ±250 pA
TA = –40°C to 125°C (1) ±5 nA
NOISE
EN Input voltage noise f = 0.1 Hz to 10 Hz   9.2 μVPP
  1.4   µVRMS
eN Input voltage noise density f = 1 kHz 37   nV/√Hz
f = 10 kHz   21  
iN Input current noise f = 1 kHz   80 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (VCC–) + 1.5 (VCC+) V
CMRR Common-mode rejection ratio VS = 40 V, (VCC–) + 2.5 V < VCM < (VCC+) – 1.5 V 100 105 dB
CMRR Common-mode rejection ratio TA = –40°C to 125°C 95 dB
CMRR Common-mode rejection ratio VS = 40 V, (VCC–) + 2.5 V < VCM < (VCC+) 90 105 dB
CMRR Common-mode rejection ratio TA = –40°C to 125°C 80 dB
INPUT CAPACITANCE
ZID Differential 100 || 2 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2,
(VCC–) + 0.3 V < VO < (VCC+) –  0.3 V
TA = –40°C to 125°C 118 125 dB
AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2, RL = 2 kΩ, (VCC–) + 1.2 V < VO < (VCC+) –  1.2 V TA = –40°C to 125°C 115 120 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product 5.25 MHz
SR Slew rate VS = 40 V, G = +1, CL = 20 pF 20 V/μs
tS Settling time To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.63 μs
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.56
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.91
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.48
Phase margin G = +1, RL = 10kΩ, CL = 20 pF 56 °
Overload recovery time VIN  × gain > VS 300 ns
THD+N Total harmonic distortion + noise VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz 0.00012 %
EMIRR EMI rejection ratio f = 1 GHz 53 dB
OUTPUT
  Voltage output swing from rail Positive rail headroom VS = 40 V, RL = 10 kΩ   115 210 mV
VS = 40 V, RL = 2 kΩ   520 965
Negative rail headroom VS = 40 V, RL = 10 kΩ   105 215
VS = 40 V, RL = 2 kΩ   500 1030
ISC Short-circuit current ±26 mA
CLOAD Capacitive load drive 300
pF
ZO Open-loop output impedance f = 1 MHz, IO = 0 A 125
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 937.5 1125 µA
IO = 0 A, (TL071H) 960 1156
IO = 0 A TA = –40°C to 125°C 1130
IO = 0 A, (TL072H) 1143
IO = 0 A, (TL071H) 1160
Turn-On Time At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs
60 μs
Max IB and Ios data is specified based on characterization results.