SLFS043I September   1983  – July 2019 TLC555


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions: D, P, PS, and JG Packages
    2.     Pin Functions: PW and FK
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I
    5. 6.5 Electrical Characteristics: VDD = 5 V
    6. 6.6 Electrical Characteristics: VDD = 15 V
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Monostable Operation
      2. 7.3.2 Astable Operation
      3. 7.3.3 Frequency Divider
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Missing-Pulse Detector
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      2. 8.2.2 Pulse-Width Modulation
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      3. 8.2.3 Pulse-Position Modulation
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 8.2.4 Sequential Timer
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      5. 8.2.5 Designing for Improved ESD Performance
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Monostable Operation

For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the internal latch; the output goes high, and discharge pin (DISCH) becomes open drain. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the internal latch, the output goes low, the discharge pin goes low which quickly discharges capacitor C.

TLC555 app_fig1_lfs022.gifFigure 9. Circuit for Monostable Operation

Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high for at least 1 µs before the end of the timing interval. When the trigger is grounded, the comparator storage time can be as long as 1 µs, which limits the minimum monostable pulse width to 1 µs. The output pulse duration is approximately tw = 1.1 × RAC. Figure 11 is a plot of the time constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VDD. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval.

Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges capacitor C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used it must be connected to VDD.

TLC555 app_fig2_lfs022.gif
RA = 9.1 kΩ CL = 0.01 µF See Figure 9
Figure 10. Typical Monostable Waveforms
TLC555 D006_MonoT4_SLFS043.gifFigure 11. Output Pulse Duration vs Capacitance