SBVS199C June   2012  – January 2024 TLC59283

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Storage Conditions
    3. 5.3 ESD Ratings
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Pin-equivalent Input and Output Schematic Diagrams
    2. 6.2 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Constant Sink Current Value Setting
      2. 7.3.2 Constant-current Driver On or Off Control
      3. 7.3.3 Noise Reduction
        1. 7.3.3.1 Internal Pre-Charge FET
        2. 7.3.3.2 Improve Output Control Loop Stability
  9. 8 Register Configuration
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Register Configuration

The TLC59283 has a 16-bit shift register and an output on or off data latch. Both the shift register and data latch are 16 bits long and are used to turn the constant-current outputs on and off. Figure 8-1 shows the shift register and data latch configuration. The data at the SIN pin are shifted into the 16-bit shift register LSB at the rising edge of the SCLK pin; SOUT data change at the SCLK rising edge.

GUID-22C8DE3F-F57F-45B3-A9DC-73F3ABCA4E98-low.gifFigure 8-1 16-Bit Shift Register and Output On or Off Data Latch Configuration

The output on or off data in the 16-bit shift register continue to transfer to the output on or off data latch while LAT is high. Therefore, if the data in the 16-bit shift register are changed when LAT is high, the data in the data latch are also changed. The data in the data latch are held when LAT is low. When the device initially powers on, the data in the output on or off shift register and latch are not set to default values; on or off control data must be written to the on or off control data latch before turning the constant-current output on. All constant-current outputs are forced off when BLANK is high. The OUTn on or off outputs are controlled by the data in the output on or off data latch. The writing data truth table and timing diagram are shown in Table 8-1 and Figure 8-2, respectively.

Table 8-1 Truth Table in Operation
SCLKLATBLANKSINOUT0…OUT7…OUT15SOUT
↑HighLowDnDn…Dn – 7…Dn – 15Dn – 15
↑LowLowDn + 1No changeDn – 14
↑HighLowDn + 2Dn + 2…Dn – 5…Dn – 13Dn – 13
↓—LowDn + 3Dn + 2…Dn – 5…Dn – 13Dn – 13
↓—HighDn + 3OffDn – 13
GUID-C0A55161-EF4C-4B34-99BF-CC55574E8FA9-low.gifFigure 8-2 Operation Timing Diagram