SLAS520E February   2007  – December 2014 TLV320AIC3101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Diagram
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Device Comparison Table
  8. 8 Pin Configuration and Functions
  9. 9 Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 ESD Ratings
    3. 9.3 Recommended Operating Conditions
    4. 9.4 Thermal Information
    5. 9.5 Electrical Characteristics
    6. 9.6 Timing Requirements: Audio Data Serial Interface
    7. 9.7 Typical Characteristics
  10. 10Parameter Measurement Information
  11. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1  Hardware Reset
      2. 11.3.2  Digital Audio Data Serial Interface
        1. 11.3.2.1 Right-Justified Mode
        2. 11.3.2.2 Left-Justified Mode
        3. 11.3.2.3 I2S Mode
        4. 11.3.2.4 DSP Mode
        5. 11.3.2.5 TDM Data Transfer
      3. 11.3.3  Audio Data Converters
        1. 11.3.3.1 Audio Clock Generation
        2. 11.3.3.2 Stereo Audio ADC
          1. 11.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 11.3.3.2.2 Automatic Gain Control (AGC)
            1. 11.3.3.2.2.1 Target Level
            2. 11.3.3.2.2.2 Attack Time
            3. 11.3.3.2.2.3 Decay Time
            4. 11.3.3.2.2.4 Noise Gate Threshold
            5. 11.3.3.2.2.5 Maximum PGA Gain Applicable
        3. 11.3.3.3 Stereo Audio DAC
          1. 11.3.3.3.1 Digital Audio Processing for Playback
          2. 11.3.3.3.2 Digital Interpolation Filter
          3. 11.3.3.3.3 Audio DAC Digital Volume Control
          4. 11.3.3.3.4 Increasing DAC Dynamic Range
          5. 11.3.3.3.5 Analog Output Common-Mode Adjustment
          6. 11.3.3.3.6 Audio DAC Power Control
      4. 11.3.4  Audio Analog Inputs
      5. 11.3.5  Analog Fully Differential Line Output Drivers
      6. 11.3.6  Analog High-Power Output Drivers
      7. 11.3.7  Input Impedance and VCM Control
      8. 11.3.8  MICBIAS Generation
      9. 11.3.9  Short-Circuit Output Protection
      10. 11.3.10 Jack/Headset Detection
    4. 11.4 Device Functional Modes
      1. 11.4.1 Bypass Path Mode
        1. 11.4.1.1 Analog Input Bypass Path Functionality
        2. 11.4.1.2 ADC PGA Signal Bypass Path Functionality
        3. 11.4.1.3 Passive Analog Bypass During Power Down
      2. 11.4.2 Digital Audio Processing for Record Path
    5. 11.5 Programming
      1. 11.5.1 I2C Control Interface
      2. 11.5.2 I2C Bus Debug in a Glitched System
    6. 11.6 Register Maps
    7. 11.7 Output Stage Volume Controls
  12. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier
        1. 12.2.1.1 Design Requirements
        2. 12.2.1.2 Detailed Design Procedure
        3. 12.2.1.3 Application Curves
      2. 12.2.2 Connections With Headphone and External Speaker Driver in Cell Phone Application
        1. 12.2.2.1 Design Requirements
        2. 12.2.2.2 Detailed Design Procedure
        3. 12.2.2.3 Application Curves
  13. 13Power Supply Recommendations
  14. 14Layout
    1. 14.1 Layout Guidelines
    2. 14.2 Layout Example
  15. 15Device and Documentation Support
    1. 15.1 Trademarks
    2. 15.2 Electrostatic Discharge Caution
    3. 15.3 Glossary
  16. 16Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Pin Configuration and Functions

RHB Package
(Bottom View)
p0048-01_las510.gif
Connect device thermal pad to DRVSS.

Pin Functions

PIN DESCRIPTION
NAME NO. I/O
AVDD 25 — Analog DAC voltage supply, 2.7 V–3.6 V
AVSS1 17 — Analog ADC ground supply, 0 V
AVSS2 26 — Analog DAC ground supply, 0 V
BCLK 2 I/O Audio serial data bus bit clock input/output
DIN 4 I Audio serial data bus data input
DOUT 5 O Audio serial data bus data output
DRVDD 18 — Analog ADC and output driver voltage supply, 2.7 V–3.6 V
DRVDD 24 — Analog output driver voltage supply, 2.7 V–3.6 V
DRVSS 21 — Analog output driver ground supply, 0 V
DVDD 32 — Digital core voltage supply, 1.525 V–1.95 V
DVSS 6 — Digital core / I/O ground supply, 0 V
HPLCOM 20 O High-power output driver (left – or multifunctional)
HPLOUT 19 O High-power output driver (left +)
HPRCOM 22 O High-power output driver (right – or multifunctional)
HPROUT 23 O High-power output driver (right +)
IOVDD 7 — Digital I/O voltage supply, 1.1 V–3.6 V
LEFT_LOM 28 O Left line output (–)
LEFT_LOP 27 O Left line output (+)
MCLK 1 I Master clock input
MIC1LM/LINE1LM 11 I Left input – (diff only)
MIC1LP/LINE1LP 10 I Left input 1 (SE) or left input + (diff)
MIC1RM/LINE1RM 13 I Right input – (diff only)
MIC1RP/LINE1RP 12 I Right input 1 (SE) or right input + (diff)
MIC2L/LINE2L/MICDET 14 I Left input 2 (SE); can support microphone detection
MIC2R/LINE2R 16 I Right input 2 (SE)
MICBIAS 15 O Microphone bias voltage output
RESET 31 I Reset
RIGHT_LOM 30 O Right line output (–)
RIGHT_LOP 29 O Right line output (+)
SCL 8 I/O I2C serial clock input
SDA 9 I/O I2C serial data input/output
WCLK 3 I/O Audio serial data bus word clock input/output