SLAS715C June 2010 – January 2023 TLV320AIC3104-Q1
PRODUCTION DATA
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. Figure 9-18 shows a timing diagram of this operation.