SLAS715C June   2010  – January 2023 TLV320AIC3104-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 8.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 8.8  Switching Characteristics DSP Timing in Master Mode
    9. 8.9  Switching Characteristics DSP Timing in Slave Mode
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Audio Data Converters
      2. 9.3.2  Stereo Audio ADC
        1. 9.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 9.3.3  Automatic Gain Control (AGC)
      4. 9.3.4  Stereo Audio DAC
      5. 9.3.5  Digital Audio Processing for Playback
      6. 9.3.6  Digital Interpolation Filter
      7. 9.3.7  Delta-Sigma Audio DAC
      8. 9.3.8  Audio DAC Digital Volume Control
      9. 9.3.9  Analog Output Common-mode Adjustment
      10. 9.3.10 Audio DAC Power Control
      11. 9.3.11 Audio Analog Inputs
      12. 9.3.12 Analog Input Bypass Path Functionality
      13. 9.3.13 ADC PGA Signal Bypass Path Functionality
      14. 9.3.14 Input Impedance and VCM Control
      15. 9.3.15 MICBIAS Generation
      16. 9.3.16 Analog Fully Differential Line Output Drivers
      17. 9.3.17 Analog High-Power Output Drivers
      18. 9.3.18 Short-Circuit Output Protection
      19. 9.3.19 Jack and Headset Detection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Audio Processing for Record Path
      2. 9.4.2 Increasing DAC Dynamic Range
      3. 9.4.3 Passive Analog Bypass During Power Down
      4. 9.4.4 Hardware Reset
    5. 9.5 Programming
      1. 9.5.1  Digital Control Serial Interface
      2. 9.5.2  I2C Control Interface
      3. 9.5.3  I2C Bus Debug in a Glitched System
      4. 9.5.4  Digital Audio Data Serial Interface
      5. 9.5.5  Right-Justified Mode
      6. 9.5.6  Left-Justified Mode
      7. 9.5.7  I2S Mode
      8. 9.5.8  DSP Mode
      9. 9.5.9  TDM Data Transfer
      10. 9.5.10 Audio Clock Generation
    6. 9.6 Register Maps
      1. 9.6.1 Output Stage Volume Controls
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.3 Automatic Gain Control (AGC)

An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (the AGC can be fully disabled if not needed). This circuitry automatically adjusts the PGA gain when the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target level, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm to be fine-tuned for any particular application. These AGC features are explained in this section, and Figure 9-1 illustrates their operation. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal.

Note: Completely independent AGC circuitry is included with each ADC channel with entirely independent control over the algorithm from one channel to the next. This is attractive in cases where two microphones are used in a system, but may have different placement in the end equipment and require different dynamic performance for optimal system operation

The TLV320AIC3104-Q1 allows programming of eight different target levels, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Because the device reacts to the signal absolute average and not to peak levels, it is recommended that the target level be set with enough margin to avoid clipping at the occurrence of loud sounds.

Attack can be varied from 7 ms to 1,408 ms. The extended right-channel attack time can be programmed by writing to page 0, register 103, and the left channel is programmed by writing to page 0, register 105.

Decay time can be varied in the range from 0.05 s to 22.4 s. The extended right-channel decay time can be programmed by writing to page 0, register 104, and the left channel is programmed by writing to page 0, register 106.

The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the clock setup that is used. Table 9-1 shows the relationship of the NCODEC ratio to the maximum time available for the AGC decay. In practice, these maximum times are extremely long for audio applications and should not limit any practical AGC decay time that is needed by the system.

Table 9-1 AGC Decay Time Restriction
NCODEC RATIO MAXIMUM DECAY TIME (SECONDS)
1 4
1.5 5.6
2 8
2.5 9.6
3 11.2
3.5 11.2
4 16
4.5 16
5 19.2
5.5 22.4
6 22.4

In this situation, the AGC considers the input signal as a silence and will set the noise threshold flag while reducing the gain down to 0 dB in steps of 0.5 dB every sample period. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This ensures that noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also available. This operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is set, the status of gain applied by the AGC and the saturation flag should be ignored.

The Maximum PGA gain applicable can be set by the user, which restricts the maximum PGA gain that can be applied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.

GUID-9449EAFB-23BB-4572-A68F-A2CA42BC9CCF-low.gifFigure 9-1 Typical Operation of the AGC Algorithm During Speech Recording
Note: The time constants here are correct when the ADC is not in double-rate audio mode. The time constants are achieved using the fS(ref) value programmed in the control registers. However, if the fS(ref) is set in the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different fS(ref) in practice, then the time constants would not be correct.

The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the clock setup that is used. Table 9-1 shows the relationship of the NCODEC ratio to the maximum time available for the AGC decay. In practice, these maximum times are extremely long for audio applications and should not limit any practical AGC decay time that is needed by the system.