SLOS545D November   2008  – December 2014 TLV320AIC3107

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Block Diagram
  5. 5 Revision History
  6. 6 Description (Continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Dissipation Ratings
    6. 8.6 Electrical Characteristics
    7. 8.7 Audio Data Serial Interface Timing Requirements
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. 10.3.2.1 Right Justified Mode
        2. 10.3.2.2 Left Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
        3. 10.3.3.3 Stereo Audio DAC
          1. 10.3.3.3.1 Digital Audio Processing for Playback
          2. 10.3.3.3.2 Digital Interpolation Filter
          3. 10.3.3.3.3 Delta-Sigma Audio DAC
          4. 10.3.3.3.4 Audio DAC Digital Volume Control
          5. 10.3.3.3.5 Increasing DAC Dynamic Range
          6. 10.3.3.3.6 Analog Output Common-Mode Adjustment
          7. 10.3.3.3.7 Audio DAC Power Control
      4. 10.3.4  Audio Analog Inputs
      5. 10.3.5  Analog Line Output Drivers
      6. 10.3.6  Analog High Power Output Drivers
      7. 10.3.7  Input Impedance and VCM Control
      8. 10.3.8  General Purpose I/O
      9. 10.3.9  MICBIAS Generation
      10. 10.3.10 Class-D Speaker Driver
      11. 10.3.11 Short Circuit Output Protection
      12. 10.3.12 Jack and Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 Analog Input Bypass Path Functionality
        2. 10.4.1.2 ADC PGA Signal Bypass Path Functionality
        3. 10.4.1.3 Passive Analog Bypass During Powerdown
      2. 10.4.2 Digital Audio Processing For Record Path
    5. 10.5 Programming
      1. 10.5.1 I2C Control Mode
        1. 10.5.1.1 I2C Bus Debug in a Glitched System
        2. 10.5.1.2 Register Map Structure
    6. 10.6 Register Maps
      1. 10.6.1 Control Registers
      2. 10.6.2 Output Stage Volume Controls
        1. 10.6.2.1 Page 1 / Register 10:   Left Channel Audio Effects Filter N4 Coefficient LSB Register
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Trademarks
    2. 14.2 Electrostatic Discharge Caution
    3. 14.3 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

11.1 Application Information

The TLV320AIC3107 is a highly integrated low-power stereo audio codec with integrated stereo headphone/line, and mono class D amplifier, as well as multiple inputs and outputs that are programmable in single-ended or fully differential configurations. All the features of the TLV320AIC3107 are accessed by programmable registers. External processor with I2C protocol is required to control the device. It is good practice to perform a hardware reset after initial power up to ensure that all registers are in their default states. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 14-mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony applications.

11.2 Typical Application

typ_con2_los545.gifFigure 37. Typical Connections for Capless Headphone and External Speaker Amp

11.2.1 Design Requirements

For this design example, use the parameters shown in Table 7.

Table 7. Design Parameters

PARAMETER VALUE
Supply Voltage (AVDD, DRVDD) 3.3 V
Supply Voltage (DVDD, IOVDD) 1.8 V
Analog High-Power Output Driver Load 16 Ω
Analog Fully Differential Line Output Driver Load 10 kΩ
Class D Audio Amplifier Load 18 Ω

11.2.2 Detailed Design Procedure

  • Use the Typical Application Schematic as a guide, integrate the hardware into the system.
  • Following the recommended component placement, schematic layout and routing given in the Figure 41 below, integrate the device and its supporting components into the system PCB.
    • For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the recommended layout, please visit the E2E forum to request a layout review.
  • Determining sample rate and Master clock frequency is required since powering up the device as all internal timing is derived from the master clock. Refer to the Audio Clock Generation section in order to get more information on how to configure correctly the required clocks for the device.
  • As the TLV320AIC3107 is designed for low-power applications, when powered up, the device has several features powered down. A correct routing of the TLV320AIC3107 signals is achieved by a correct setting of the device registers, powering up the required stages of the device and configuring the internal switches to follow a desired route.
  • For more information of the device configuration and programming, refer to the TLV320AIC3107 technical documents section in ti.com (http://www.ti.com/product/TLV320AIC3105/technicaldocuments).

11.2.3 Application Curves

thd1_op_las509.gifFigure 38. Total Harmonic Distortion vs Headphone Out Power
mbias_v_las509.gifFigure 39. MICBIAS Voltage vs Supply Voltage