SNOSDA2E august   2020  – july 2023 TLV3604 , TLV3605 , TLV3607

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Configurations: TLV3604 and TLV3605
    2. 5.1 Pin Configuration: TLV3607
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics (VCCI = VCCO = 2.5 V to 5 V)
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Rail-to-Rail Inputs
      2. 7.4.2 LVDS Output
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Comparator Inputs
      2. 8.1.2 Capacitive Loads
      3. 8.1.3 Latch Functionality
      4. 8.1.4 Adjustable Hysteresis
    2. 8.2 Typical Application
      1. 8.2.1 Non-Inverting Comparator With Hysteresis
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Optical Receiver
      3. 8.2.3 Logic Clock Source to LVDS Transceiver
      4. 8.2.4 External Trigger Function for Oscilloscopes
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

The TLV3604 has a single functional mode and is operational when the power supply voltage is greater than
the minimum operating voltage. On the other hand, the TLV3605 and TLV3607 have an active and shutdown mode. The TLV3605 and TLV3607 are in shutdown mode when the SHDN pin is logic low. To allow for easy interface with 1.8V FPGAs and CPUs, the SHDN pin is 1.8 V logic compliant and independent of the comparator power supply.