SLUSDR2A December   2020  – January 2023 TLV62595

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse Width Modulation (PWM) Operation
      2. 7.3.2 Power Save Mode (PSM) Operation
      3. 7.3.3 Minimum Duty Cycle and 100% Mode Operation
      4. 7.3.4 Soft Start
      5. 7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Disable and Output Discharge
      2. 7.4.2 Power Good
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting The Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = High, no load, device not switching 10 µA
ISD Shutdown current EN = Low, TJ = -40 ℃ to 85 ℃ 0.05 µA
VUVLO Under voltage lock out threshold VIN falling 2.1 2.2 2.3 V
Under voltage lock out hysteresis VIN rising 160 mV
TJSD Thermal shutdown threshold TJ rising 150 °C
Thermal shutdown hysteresis TJ falling 20 °C
LOGIC INTERFACE EN
VIH High-level threshold voltage VIN = 2.5 V to 5.5 V 1.0 V
VIL Low-level threshold voltage VIN = 2.5 V to 5.5 V 0.4 V
SOFT START, POWER GOOD
tSS Soft start time Time from EN high to 95% of VOUT nominal 1.75 ms
VPG Power good lower threshold VPG rising, VFB referenced to VFB nominal 96 %
VPG falling, VFB referenced to VFB nominal 92 %
Power good upper threshold VPG rising, VFB referenced to VFB nominal 105 %
VPG falling, VFB referenced to VFB nominal 110 %
VPG,OL Low-level output voltage Isink = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5.0 V 0.01 µA
tPG,DLY Power good deglitch delay PG rising edge 100 µs
PG falling edge 20
OUTPUT
VFB Feedback regulation voltage PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, TJ = -40°C to 125°C 594 600 606 mV
IFB,LKG Feedback input leakage current for adjustable output voltage VFB = 0.6 V 0.01 µA
IDIS Output discharge current VSW = 0.4V; EN = LOW 400 mA
Load regulation IOUT = 0.5 A to 3 A, VOUT = 1.8 V 0.1 %/A
POWER SWITCH
RDS(on) High-side FET on-resistance 26 mΩ
Low-side FET on-resistance 25 mΩ
ILIM High-side FET switch current limit, DC 4.8 5.6 A
fSW PWM switching frequency IOUT = 1 A, VOUT = 1.8 V 2.2 MHz