SLVSC35D August 2013 – July 2019 TLV702-Q1
The TLV702-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear (triode) region of operation. The input-to-output resistance is equal to the drain-source on-state resistance (RDS(on)) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 13.