Figure 9-2 and Figure 9-3 show the TLV803EA29 functionality. In Figure 9-2, the VDD supply voltage drops from 30% above VIT- = 3.8 V to 10% below VIT- = 2.6 V with a 0.1-µF capacitor on VDD. The RESET output is connected to VDD through the pull-up resistor so when the VDD supply voltage drops. The RESET output discharges down to the VDD supply voltage through the pull-up resistor and RESET pin capacitance. Once the high-to-low propagation delay tPD_HL expires, the internal MOSFET turns on and asserts RESET to logic low. Note that tPD_HL varies with VDD specifically on how much VDD drops and how quickly in addition to the VDD and RESET pin capacitances. In Figure 9-3, VDD rises from 2 V to 4 V and the RESET output deasserts to logic high after the reset delay time (tD) expires.