SBOSA68D November   2021  – March 2024 TLV9161 , TLV9162 , TLV9164

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Protection Circuitry
      2. 6.3.2  EMI Rejection
      3. 6.3.3  Thermal Protection
      4. 6.3.4  Capacitive Load and Stability
      5. 6.3.5  Common-Mode Voltage Range
      6. 6.3.6  Phase Reversal Protection
      7. 6.3.7  Electrical Overstress
      8. 6.3.8  Overload Recovery
      9. 6.3.9  Typical Specifications and Distributions
      10. 6.3.10 Packages With an Exposed Thermal Pad
      11. 6.3.11 Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Buffered Multiplexer
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-09C85506-E6BB-4BE1-937B-07BEBF4AC850-low.svgFigure 4-1 TLV9161 DBV Package
5-Pin SOT-23
(Top View)
GUID-EE7B09D3-CEAC-4586-9A9B-7F5170327C21-low.svgFigure 4-2 TLV9161 DCK Package
5-Pin SC70
(Top View)
Table 4-1 Pin Functions: TLV9161
PIN I/O DESCRIPTION
NAME SOT-23 SC70
IN+ 3 1 I Noninverting input
IN– 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply
GUID-1823D142-DF18-492B-A306-704965F0A747-low.gif Figure 4-3 TLV9161S DBV Package
6-Pin SOT-23
(Top View)
Table 4-2 Pin Functions: TLV9161S
PIN I/O DESCRIPTION
NAME NO.
+IN 3 I Noninverting input
–IN 4 I Inverting input
OUT 1 O Output
SHDN 5 I Shutdown: low = amplifier enabled, high = amplifier disabled
V+ 6 — Positive (highest) power supply
V– 2 — Negative (lowest) power supply
GUID-C4D6F777-BA62-4FE3-9AFB-B9BDB29304DF-low.svgFigure 4-4 TLV9162 D, DDF, PW, and DGK Package
8-Pin SOIC, SOT-23, TSSOP, and VSSOP
(Top View)
GUID-CF7D304A-A85F-4D15-AFAD-ED29A4A434C2-low.svg
A. Connect thermal pad to V–. See Section 6.3.10 for more information.
Figure 4-5 TLV9162 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
(Top View)
Table 4-3 Pin Functions: TLV9162
PIN I/O DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
GUID-5DA6B7F4-2EBB-43D1-B812-3BBD384B1F79-low.gif Figure 4-6 TLV9162S RUG Package
10-Pin X2QFN
(Top View)
Table 4-4 Pin Functions: TLV9162S
PIN I/O DESCRIPTION
NAME NO.
IN1+ 10 I Noninverting input, channel 1
IN1– 9 I Inverting input, channel 1
IN2+ 4 I Noninverting input, channel 2
IN2– 5 I Inverting input, channel 2
OUT1 8 O Output, channel 1
OUT2 6 O Output, channel 2
SHDN1 2 I Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See Section 6.3.11 for more information.
SHDN2 3 I Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See Section 6.3.11 for more information.
V+ 7 — Positive (highest) power supply
V– 1 — Negative (lowest) power supply
GUID-0E67BA56-837A-453D-8CCB-9EA49A450988-low.svgFigure 4-7 TLV9164 D and PW Package
14-Pin SOIC and TSSOP
(Top View)
Table 4-5 Pin Functions: TLV9164
PIN I/O DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply