SBOSA68D November   2021  – March 2024 TLV9161 , TLV9162 , TLV9164

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Protection Circuitry
      2. 6.3.2  EMI Rejection
      3. 6.3.3  Thermal Protection
      4. 6.3.4  Capacitive Load and Stability
      5. 6.3.5  Common-Mode Voltage Range
      6. 6.3.6  Phase Reversal Protection
      7. 6.3.7  Electrical Overstress
      8. 6.3.8  Overload Recovery
      9. 6.3.9  Typical Specifications and Distributions
      10. 6.3.10 Packages With an Exposed Thermal Pad
      11. 6.3.11 Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Buffered Multiplexer
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision C (January 2024) to Revision D (March 2024)

  • Added PSRR values for TLV9162SIRUGRGo

Changes from Revision B (August 2022) to Revision C (January 2024)

  • Removed preview notation from TLV9164 X2QFN (10) package from Device Information tableGo

Changes from Revision A (December 2021) to Revision B (August 2022)

  • Added TLV9162 X2QFN (10) package to Device Information table with preview statusGo
  • Added TLV9162 X2QFN package (RUG) to the Pin Configuration and Functions section with preview statusGo
  • Added VIH and VIL in Recommended Operating Conditions sectionGo
  • Added SHUTDOWN in Electrical Characteristics tableGo

Changes from Revision * (November 2021) to Revision A (December 2021)

  • Removed preview notation from TLV9164 SOIC (14) package from Device Information tableGo
  • Removed preview notation from TLV9164 TSSOP (14) package from Device Information tableGo
  • Removed preview notation from TLV9164 D package (SOIC) in the Pin Configuration and Functions sectionGo
  • Removed preview notation from TLV9164 PW package (TSSOP) in the Pin Configuration and Functions sectionGo
  • Removed preview notation from TLV9164 D package (SOIC) in the Thermal Information for Quad Channel sectionGo
  • Removed preview notation from TLV9164 PW package (TSSOP) in the Thermal Information for Quad Channel sectionGo
  • Added PSRR specification for TLV9164 release in Electrical Characteristics sectionGo
  • Added clarification to VS = 2.7 V to 16 V PSRR specification noting that specification is for all channel variantsGo