SPRS727C August   2012  – April 2014 TMS320C5517


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. 4.2.1  Oscillator and PLL
      2. 4.2.2  Real-Time Clock (RTC)
      3. 4.2.3  RESET, Interrupts, and JTAG
      4. 4.2.4  External Memory Interface (EMIF)
      5. 4.2.5  Inter-Integrated Circuit (I2C)
      6. 4.2.6  Inter-IC Sound (I2S)
      7. 4.2.7  Multichannel Buffered Serial Port (McBSP)
      8. 4.2.8  Multichannel Serial Port Interface (McSPI)
      9. 4.2.9  Serial Peripheral Interface (SPI)
      10. 4.2.10 Universal Asynchronous Receiver and Transmitter (UART)
      11. 4.2.11 Universal Serial Bus (USB) 2.0
      12. 4.2.12 Universal Host-Port Interface (UHPI)
      13. 4.2.13 MultiMedia Card (MMC)
      14. 4.2.14 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
      15. 4.2.15 General-Purpose Input and Output (GPIO)
      16. 4.2.16 Regulators and Power Management
      17. 4.2.17 Supply Voltage
      18. 4.2.18 Ground
    3. 4.3 Pin Multiplexing
      1. 4.3.1 UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing [EBSR.PPMODE Bits]
      2. 4.3.2 MMC1, McSPI, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
      3. 4.3.3 MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
      4. 4.3.4 EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits]
    4. 4.4 Connections for Unused Signals
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Electrical Characteristics
      1. 5.3.1 Power Consumption
      2. 5.3.2 Electrical Characteristics
    4. 5.4 Handling Ratings
    5. 5.5 Thermal Characteristics
    6. 5.6 Power-On Hours
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  Parameter Information
        1. 1.8-V, 2.75-V, and 3.3-V Signal Transition Levels
        2. 3.3-V Signal Transition Rates
        3. Timing Parameters and Board Routing Analysis
      2. 5.7.2  Power Supplies
        1. Power Considerations
          1. LDO Configuration
            1. LDO Inputs
            2. LDO Outputs
              1. LDO Control
        2. Power-Supply Sequencing
        3. Digital I/O Behavior When Core Power (CVDD) is Down
        4. Power-Supply Design Considerations
        5. Power-Supply Decoupling
        6. LDO Input Decoupling
        7. LDO Output Decoupling
      3. 5.7.3  Reset
        1. Power-On Reset (POR) Circuits
          1. RTC Power-On Reset (POR)
          2. Main Power-On Reset (POR)
          3. Reset Pin (RESET)
        2. Pin Behavior at Reset
        3. Reset Electrical Data and Timing
        4. Configurations at Reset
          1. Device and Peripheral Configurations at Device Reset
          2. BootMode Implementation and Requirements
        5. Configurations After Reset
          1. External Bus Selection Register (EBSR)
          2. LDO Control Register [7004h]
          3. EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h]
          4. Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
          5. Pullup and Pulldown Inhibit Registers (PUDINHIBR1, 2, 3, 4, 5, 6, and 7) [1C17h, 1C18h, 1C19h, 1C4Ch, 1C4Dh, 1C4Fh, and 1C50h, respectively]
          6. Output Slew Rate Control Register (OSRCR) [1C16h]
      4. 5.7.4  Clock Specifications
        1. Recommended Clock and Control Signal Transition Behavior
        2. Clock Considerations
          1. Clock Configurations After Device Reset
            1. Device Clock Frequency
            2. Peripheral Clock State
            3. USB Oscillator Control
        3. PLLs
          1. PLL Device-Specific Information
          2. Clock PLL Considerations With External Clock Sources
          3. External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins
            1. USB On-Chip Oscillator With External Crystal
            2. Real-Time Clock (RTC) On-Chip Oscillator With External Crystal
            3. CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)
        4. Input and Output Clocks Electrical Data and Timing
        5. Wake-up Events, Interrupts, and XF
          1. Interrupts Electrical Data and Timing
          2. Wake-Up From IDLE Electrical Data and Timing
          3. XF Electrical Data and Timing
      5. 5.7.5  Direct Memory Access (DMA) Controller
        1. DMA Channel Synchronization Events
      6. 5.7.6  External Memory Interface (EMIF)
        1. EMIF Asynchronous Memory Support
        2. EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported
        3. EMIF Electrical Data and Timing CVDD = 1.05 V, DVDDEMIF = 3.3/2.75/1.8 V
        4. EMIF Electrical Data and Timing CVDD = 1.3/1.4 V, DVDDEMIF = 3.3/2.75/1.8 V
      7. 5.7.7  General-Purpose Input/Output (GPIO)
        1. GPIO Peripheral Input/Output Electrical Data and Timing
        2. GPIO Peripheral Input Latency Electrical Data and Timing
      8. 5.7.8  Inter-Integrated Circuit (I2C)
        1. I2C Electrical Data and Timing
      9. 5.7.9  Inter-IC Sound (I2S)
        1. Inter-IC Sound (I2S) Electrical Data and Timing
      10. 5.7.10 Multichannel Serial Port Interface (McSPI)
        1. McSPI Electrical Data and Timing
          1. McSPI in Slave Mode
          2. McSPI in Master Mode
      11. 5.7.11 Multichannel Buffered Serial Port (McBSP)
        1. McBSP Electrical Data and Timing
      12. 5.7.12 Multimedia Card and Secure Digital (eMMC, MMC, SD, and SDHC)
        1. MMC and SD Electrical Data and Timing
      13. 5.7.13 Real-Time Clock (RTC)
        1. RTC Electrical Data and Timing
      14. 5.7.14 SAR ADC (10-Bit)
        1. SAR ADC Electrical Data and Timing
      15. 5.7.15 Serial Port Interface (SPI)
        1. SPI Electrical Data and Timing
      16. 5.7.16 Timers
      17. 5.7.17 Universal Asynchronous Receiver and Transmitter (UART)
        1. UART Electrical Data and Timing [Receive and Transmit]
      18. 5.7.18 Universal Host-Port Interface (UHPI)
        1. UHPI Electrical Data and Timing
      19. 5.7.19 Universal Serial Bus (USB) 2.0 Controller
        1. USB 2.0 Electrical Data and Timing
      20. 5.7.20 Emulation and Debug
        1. Debugging Considerations
          1. Pullup and Pulldown Resistors
          2. Bus Holders
          3. CLKOUT Pin
      21. 5.7.21 IEEE 1149.1 JTAG
        1. JTAG Test_port Electrical Data and Timing
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Memory
      1. 6.2.1 Internal Memory
        1. On-Chip Dual-Access RAM (DARAM)
        2. On-Chip Single-Access RAM (SARAM)
        3. On-Chip Read-Only Memory (ROM)
        4. I/O Memory
      2. 6.2.2 External Memory
      3. 6.2.3 Memory Map
      4. 6.2.4 Register Map
        1.  DMA Peripheral Register Description
        2.  EMIF Peripheral Register Description
        3.  GPIO Peripheral Register Description
        4.  I2C Peripheral Register Description
        5.  I2S Peripheral Register Description
        6.  McBSP Peripheral Register Descriptions
        7.  McSPI Peripheral Register Descriptions
        8.  MMC and SD Peripheral Register Description
        9.  RTC Peripheral Register Description
        10. SAR ADC Peripheral Register Description
        11. SPI Peripheral Register Descriptions
        12. System Registers
        13. Timers Peripheral Register Description
        14. UART Peripheral Register Description
        15. UHPI Peripheral Register Descriptions
        16. USB2.0 Peripheral Register Descriptions
    3. 6.3 Identification
      1. 6.3.1 JTAG Identification
    4. 6.4 Boot Modes
      1. 6.4.1 Invocation Sequence
      2. 6.4.2 DSP Resources Used By the Bootloader
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCH|196
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • CORE:
    • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor
      • 13.33- to 5-ns Instruction Cycle Time
      • 75- to 200-MHz Clock Rate
      • One or Two Instructions Executed per Cycle
      • Dual Multiply-and-Accumulate Units (Up to 450 Million Multiply-Accumulates per Second [MMACS])
      • Two Arithmetic and Logic Units (ALUs)
      • Three Internal Data or Operand Read Buses and Two Write Buses
      • Software-Compatible with C55x Devices
      • Industrial Temperature Devices Available
    • 320KB of Zero-Wait State On-Chip RAM:
      • 64KB of Dual-Access RAM (DARAM),
        8 Blocks of 4K x 16-Bit
      • 256KB of Single-Access RAM (SARAM),
        32 Blocks of 4K x 16-Bit
    • 128KB of Zero Wait-State On-Chip ROM
      (4 Blocks of 16K x 16-Bit)
    • Tightly Coupled FFT Hardware Accelerator
    • One Universal Host-Port Interface (UHPI) with 16-Bit Muxed Address or Data Bus
    • Master and Slave Multichannel Serial Ports Interface (McSPI) with Three Chip Selects
    • Master and Slave Multichannel Buffered Serial Ports Interface (McBSP)
    • 16- and 8-Bit External Memory Interface (EMIF) with Glueless Interface to:
      • 8- or 16-Bit NAND Flash, 1- or 4-Bit ECC
      • 8- and 16-Bit NOR Flash
      • Asynchronous Static RAM (SRAM)
      • SDRAM or mSDRAM (1.8, 2.75, and 3.3 V)
    • 3.84375M x 16-Bit Maximum Addressable External Memory Space (SDRAM or mSDRAM)
    • Universal Asynchronous Receiver/Transmitter (UART)
    • Device USB Port with Integrated 2.0 High-Speed PHY that Supports:
      • USB 2.0 Full- and High-Speed Devices
    • Direct Memory Access (DMA) Controller
      • Four DMA with Four Channels Each
    • Three 32-Bit General-Purpose (GP) Timers
      • One Selectable as a Watchdog or GP
      • Clocking Options, Including External General-Purpose I/O (GPIO) Clock Input
    • Two MultiMedia Card and Secure Digital (eMMC, MMC, and SD) Interfaces
    • Serial Port Interface (SPI) with Four Chip Selects
    • Master and Slave Inter-Integrated Circuit (I2C Bus)
    • Three Inter-IC Sound (I2S Bus) Modules for Data Transport
    • 10-Bit 4-Input Successive Approximation (SAR) ADC
    • IEEE-1149.1 (JTAG)
    • Up to 26 GPIO Pins (Multiplexed with Other Functions)
  • POWER:
    • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
    • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
    • 1.05-V Core, 1.8-, 2.75-, or 3.3-V I/Os
    • 1.3-V Core, 1.8-, 2.75-, or 3.3-V I/Os
    • 1.4-V Core, 1.8-, 2.75-, or 3.3-V I/Os
  • CLOCK:
    • Real-Time Clock (RTC) with Crystal Input, Separate Clock Domain, and Power Supply
    • Software-Programmable Phase-Locked Loop (PLL) Clock Generator
    • On-Chip ROM Bootloader
      • Each Peripheral Supports Unencrypted Booting
    • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix), 0.65-mm Pitch

1.2 Applications

  • Digital Two-Way Radios
  • Low-Power Analytics Applications (such as Speech Recognition, Vision Sensing, and Fingerprint Biometrics)
  • Voice Applications (such as Voice Recorders, Hands-Free Kits, and Voice-Enhancement Subsystems)
  • Audio Devices (such as Echo-Cancellation Headphones and Speakerphones or Wireless Headsets and Microphones)
  • Portable Medical Devices

1.3 Description

This device is a member of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low active and standby power consumption.

The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status, interrupts, and bit I/O for keyboards, and media interfaces.

Serial media is supported through two multimedia card and secure digital (MMC and SD) peripherals, three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one master and slave multichannel serial port interface (McSPI) with up to three chip selects, one multichannel serial port (McBSP), one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).

Additional peripherals include a configurable 16-bit universal host-port interface (UHPI), a high-speed universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

The device also includes a tightly coupled FFT hardware accelerate that supports 8- to 1024-point (by power of 2) real- and complex-valued FFTs and three integrated LDOs to power different sections of the device, except CVDDRTC which requires an external power source: ANA_LDO to provide 1.3 V to the SAR and power-management circuits (VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed, and USB_LDO to provide 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and a large third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

Device Information

TMS320C5517AZCH20 NFBGA (196) 10.0 mm x 10.0 mm
TMS320C5517AZCHA20 NFBGA (196) 10.0 mm x 10.0 mm

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

fbd_5525_sprs727.gifFigure 1-1 Functional Block Diagram