This device is a member of TI's C5000 fixed-point
Digital Signal Processor (DSP) product family and is designed for low active and standby power
The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP
architecture achieves high performance and low power through increased parallelism and total focus
on power savings. The CPU supports an internal bus structure that is composed of one program bus,
one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and
additional buses dedicated to peripheral and DMA activity. These buses provide the ability to
perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also
includes four DMA controllers, each with 4 channels, providing data movement for 16 independent
channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer
per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x
17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic
unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set
control, providing the ability to optimize parallel activity and power consumption. These resources
are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density.
The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and
queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to
the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability
avoids pipeline flushes on execution of conditional instructions.
The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status,
interrupts, and bit I/O for keyboards, and media interfaces.
Serial media is supported through two multimedia card and secure digital (MMC and SD)
peripherals, three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to
four chip selects, one master and slave multichannel serial port interface (McSPI) with up to three
chip selects, one multichannel serial port (McBSP), one I2C multimaster
and slave interface, and a universal asynchronous receiver/transmitter (UART) interface
The device peripheral set includes an external memory interface (EMIF) that provides
glueless access to asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to
high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).
Additional peripherals include a configurable 16-bit universal host-port interface
(UHPI), a high-speed universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three
general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop
(APLL) clock generator.
The device also includes a tightly coupled FFT hardware accelerate that supports 8- to
1024-point (by power of 2) real- and complex-valued FFTs and three integrated LDOs to power
different sections of the device, except CVDDRTC which requires an external
power source: ANA_LDO to provide 1.3 V to the SAR and power-management circuits
(VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core
(CVDD), selectable on-the-fly by software as long as operating frequency
ranges are observed, and USB_LDO to provide 1.3 V to the USB core digital
(USB_VDD1P3) and PHY circuits (USB_VDDA1P3).
The device is supported by the industry’s award-winning eXpressDSP, Code Composer Studio
Integrated Development Environment (IDE), DSP/BIOS, Texas
Instruments’ algorithm standard, and a large third-party network. Code Composer Studio IDE features
code generation tools including a C Compiler and Linker, RTDX,
XDS100, XDS510, XDS560
emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP
library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs,
and various math functions) as well as chip support libraries.