SPRS727C Data sheet

SPRS727C August 2012 – April 2014 TMS320C5517

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ZCH|196

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5 Specifications

For the device maximum operating frequency, see Section 7.1.2, Device Nomenclature.

5.1 Absolute Maximum Ratings

Over Operating Case Temperature Range (Unless Otherwise Noted)⁽¹⁾

Supply voltage ranges:	Digital Core (CV_DD, CV_DDRTC, USB_V_DD1P3)⁽²⁾	–0.5 V to 1.7 V
	I/O, 1.8 V, 2.75 V, 3.3 V (DV_DDIO, DV_DDEMIF, DV_DDRTC) 3.3V USB supplies USB PHY (USB_V_DDOSC, USB_V_DDPLL, USB_V_DDA3P3)⁽²⁾	–0.5 V to 4.2 V
	LDOI	–0.5 V to 4.2 V
	Analog, 1.3 V (V_{DDA_PLL}, USB_V_DDA1P3, V_{DDA_ANA})⁽²⁾	–0.5 V to 1.7 V
Input and Output voltage ranges:	V_I I/O, All pins with DV_DDIO or DV_DDEMIF or USB_V_DDOSC or USB_V_DDPLL or USB_V_DDA3P3 as supply source	–0.5 V to 4.2 V
	V_O I/O, All pins with DV_DDIO or DV_DDEMIF or USB_V_DDOSC or USB_V_DDPLLor USB_V_DDA3P3 as supply source	–0.5 V to 4.2 V
	RTC_XI and RTC_XO	–0.5 V to 1.7 V
	V_I and V_O, GPAIN[0]	–0.5 V to 4.2 V
	V_I and V_O, GPAIN[3:1]	–0.5 V to 1.7 V
	V_O, BG_CAP	–0.5 V to 1.7 V
	ANA_LDOO, DSP_LDOO, and USB_LDOO	–0.5 V to 1.7 V
	USB_V_BUS Input	0 V to 5.5 V
Operating case temperature ranges, T_c:	Commercial Temperature (default)	-10°C to 70°C
	Industrial Temperature	-40°C to 85°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS.

5.2 Recommended Operating Conditions

				MIN	NOM	MAX	UNIT
	CV_DD	Supply voltage, Digital Core Slew rate < 200 µs for full swing	75 MHz	0.998	1.05	1.15	V
	CV_DD		175 MHz	1.24	1.3	1.43	V

			200 MHz	1.33	1.4	1.47	V
Core Supplies	CV_DDRTC	Supply voltage, RTC and RTC OSC	32.768 kHz	0.998		CV_DD	V
	USB_V_DD1P3	Supply voltage, Digital USB		1.24	1.3	1.43	V
	USB_V_DDA1P3	Supply voltage, 1.3 V Analog USB		1.24	1.3	1.43	V
	V_{DDA_ANA}	Supply voltage, 1.3 V SAR and Pwr Mgmt		1.24	1.3	1.43	V
	V_{DDA_PLL}	Supply voltage, System PLL		1.24	1.3	1.43	V
	USB_V_DDPLL	Supply voltage, 3.3 V USB PLL		2.97	3.3	3.63	V
I/O Supplies	DV_DDIO DV_DDEMIF DV_DDRTC	Supply voltage, I/O, 3.3 V		2.97	3.3	3.63	V
		Supply voltage, I/O, 2.75 V		2.48	2.75	3.02	V
		Supply voltage, I/O, 1.8 V		1.65	1.8	1.98	V
	USB_V_DDOSC	Supply voltage, I/O, 3.3 V USB OSC		2.97	3.3	3.63	V
	USB_V_DDA3P3	Supply voltage, I/O, 3.3 V Analog USB PHY		2.97	3.3	3.63	V
	LDOI	Supply voltage, Analog Pwr Mgmt and LDO Inputs		1.8		3.6	V
GND	V_SS	Supply ground, Digital I/O		0	0	0	V
	V_SSRTC	Supply ground, RTC
	USB_V_SSOSC	Supply ground, USB OSC
	USB_V_SSPLL	Supply ground, USB PLL
	USB_V_SSA3P3	Supply ground, 3.3 V Analog USB PHY
	USB_V_SSA1P3	Supply ground, USB 1.3 V Analog USB PHY
	USB_V_SSREF	Supply ground, USB Reference Current
	V_{SSA_PLL}	Supply ground, System PLL
	USB_V_SS1P3	Supply ground, 1.3 V Digital USB PHY
	V_{SSA_ANA}	Supply ground, SAR and Pwr Mgmt
V_IH⁽¹⁾		High-level input voltage, 3.3, 2.75, 1.8 V I/O (except GPAIN[3:0] pins) ⁽²⁾		0.7 * DV_DD		DV_DD + 0.3	V
V_IL⁽¹⁾		Low-level input voltage, 3.3, 2.75, 1.8 V I/O (except GPAIN[3:0] pins) ⁽²⁾		-0.3		0.3 * DV_DD	V
V_IN		Input voltage, GPAIN0 pin⁽³⁾		-0.3		3.6	V
V_IN		Input voltage, GPAIN[3:1] pins		-0.3		V_{DDA_ANA} + 0.3	V
T_c		Operating case temperature	Commercial (default)	-10		70	°C
T_c		Operating case temperature	Industrial	-40		85	°C
F_SYSCLK		DSP Operating Frequency (SYSCLK)	1.05 V	0		75	MHz
F_SYSCLK		DSP Operating Frequency (SYSCLK)	1.3 V	0		175	MHz
			1.4 V	0		200	MHz

(1) DV_DD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 4.2, Signal Descriptions.

(2) The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could potentially draw current when the DV_DDIO is powered down. Due to the fact that different voltage devices can be connected to I2C bus and the I2C inputs are LVCMOS, the level of logic 0 (low) and logic 1 (high) are not fixed and depend on DV_DDIO.

(3) The GNDON bit in the SARPINCTRL register should be set to "1" before SAR channels 0, 1, or 2 are enabled via the CHSEL bit in the SARCTRL register, when V_IN greater than V_{DDA_ANA}.

5.3 Electrical Characteristics

5.3.1 Power Consumption

NOTE

Power consumption on this device depends on several operating parameters such as operating voltage, operating frequency, and temperature. Power consumption also varies by end applications that determine the overall processor, CPU, and peripheral activity. For more specific power consumption details, see Estimating Power Consumption on the TMS320C5517 Digital Signal Processor [literature number SPRABV3]. This document includes a spreadsheet for estimating power based on parameters that closely resemble the end application to generate a realistic estimate of power consumption on this device based on use-case and operating conditions.

5.3.2 Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)

PARAMETER		TEST CONDITIONS ⁽¹⁾		MIN	TYP	MAX	UNIT
V_OH	Full speed: USB_DN and USB_DP⁽⁷⁾			2.8		USB_V_DDA3P3	V
	High speed: USB_DN and USB_DP⁽⁷⁾			360		440	mV
	High-level output voltage, 3.3, 2.75, 1.8 V I/O (except GPAIN[3:0] pins)	IO = I_OH		0.8 * DV_DD			V
	High-level output voltage, GPAIN[3:1] pins	IO = I_OH		0.8 * V_{DDA_ANA}			V
V_OL	Full speed: USB_DN and USB_DP⁽⁷⁾			0.0		0.3	V
	High speed: USB_DN and USB_DP⁽⁷⁾			–10		10	mV
	Low-level output voltage, 3.3, 2.75, 1.8V I/O (except I2C and GPAIN[3:0] pins)	IO = I_OL				0.2 * DV_DD	V
	Low-level output voltage, I2C pins⁽³⁾	V_DD> 2 V, I_O_L= 3 mA		0		0.4	V
	Low-level output voltage, GPAIN[3:0] pins	IO = I_OL				0.2 * V_{DDA_ANA}	V
V_HYS	Input hysteresis⁽²⁾	DV_DD= 3.3 V			162		mV
V_HYS	Input hysteresis⁽²⁾	DV_DD= 1.8 V			122		mV
V_LDO	USB_LDOO voltage			1.24	1.3	1.43	V
	ANA_LDOO voltage			1.24	1.3	1.43	V
	DSP_LDOO voltage	DSP_LDO_V bit in the LDOCNTL register = 1		1.24	1.3	1.43	V
	DSP_LDOO voltage	DSP_LDO_V bit in the LDOCNTL register = 0		0.998	1.05	1.15	V
I_SD	DSP_LDO shutdown current⁽⁶⁾	LDOI = V_MIN		250			mA
	ANA_LDO shutdown current⁽⁶⁾	LDOI = V_MIN		4			mA
	USB_LDO shutdown current⁽⁶⁾	LDOI = V_MIN		25			mA
I_ILPU⁽⁸⁾⁽¹⁰⁾	Input current [DC] (except WAKEUP, I2C, and GPAIN[3:0] pins)	Input only pin, internal pulldown or pullup disabled		–5		+5	µA
		DV_DD = 3.3 V with internal pullup enabled⁽⁴⁾			–59 to –161		µA
		DV_DD = 1.8 V with internal pullup enabled⁽⁴⁾			–14 to –44		µA
I_IHPD⁽⁸⁾⁽¹⁰⁾	Input current [DC] (except WAKEUP, I2C, and GPAIN[3:0] pins)	Input only pin, internal pulldown or pullup disabled		–5		+5	µA
		DV_DD = 3.3 V with internal pulldown enabled⁽⁴⁾			52 to 158		µA
		DV_DD = 1.8 V with internal pulldown enabled⁽⁴⁾			11 to 35		µA
I_IH/ I_IL⁽¹⁰⁾	Input current [DC], ALL pins	V_I = V_SS to DV_DD with internal pullups and pulldowns disabled.		–5		+5	µA
I_OH⁽¹⁰⁾	High-level output current [DC]	All Pins (except USB, EMIF, CLKOUT, and GPAIN[3:0] pins)		–4			mA
		EMIF pins	DV_DD = 3.3 V	–6			mA
		EMIF pins	DV_DD = 1.8 V	–5			mA
		CLKOUT pin	DV_DD = 3.3 V	–6			mA
		CLKOUT pin	DV_DD = 1.8 V	–4			mA
		GPAIN[3:1] pins (GPAIN0 is open-drain and cannot drive high)	DV_DD = V_{DDA_ANA}= 1.3V, External Regulator⁽⁵⁾	–4			mA
			DV_DD = V_{DDA_ANA}= 1.3 V, Internal Regulator⁽⁵⁾	–100			µA
I_OL⁽¹⁰⁾	Low-level output current [DC]	All Pins (except USB, EMIF, CLKOUT, and GPAIN[3:0] pins)				+4	mA
		EMIF pins	DV_DD = 3.3 V			+6	mA
		EMIF pins	DV_DD = 1.8 V			+5	mA
		CLKOUT pin	DV_DD = 3.3 V			+6	mA
		CLKOUT pin	DV_DD = 1.8 V			+4	mA
		GPAIN[3:0]	DV_DD = V_{DDA_ANA}= 1.3 V, external regulator			+4	mA
		GPAIN[3:0]	DV_DD = V_{DDA_ANA}= 1.3 V, internal regulator⁽⁵⁾			+4	mA
I_OZ⁽⁹⁾	I/O Off-state output current	All Pins (except USB and GPAIN[3:0])		–10		+10	µA
I_OZ⁽⁹⁾	I/O Off-state output current	GPAIN[3:0] pins		–10		+10	µA
I_OLBH⁽¹¹⁾	Bus Holder pull low current when CV_DD is powered "OFF"	Supply voltage, I/O, 3.3 V				2.2	mA
		Supply voltage, I/O, 2.75 V				1.6	mA
		Supply voltage, I/O, 1.8 V				0.72	mA
I_OHBH⁽¹¹⁾	Bus Holder pull high current when CV_DD is powered "OFF"	Supply voltage, I/O, 3.3 V		–1.3			mA
		Supply voltage, I/O, 2.75 V		–0.97			mA
		Supply voltage, I/O, 1.8 V		–0.46			mA
		V_{DDA_PLL}= 1.3 V Room Temp, Phase detector = 12 MHz, VCO = 125 MHz			0.93
I	Analog PLL (V_{DDA_PLL}) supply current	V_{DDA_PLL}= 1.3 V Room Temp, Phase detector = 12 MHz, VCO = 175 MHz			1.23		mA
		V_{DDA_PLL}= 1.3 V Room Temp, Phase detector = 12 MHz, VCO = 200 MHz			1.54

	SAR Analog (V_{DDA_ANA}) supply current	V_{DDA_ANA}= 1.3 V, SAR clock = 2 MHz, Temp (70 °C)				1	mA
C_I	Input capacitance					4	pF
C_o	Output capacitance					4	pF

(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

(2) Applies to all input pins except WAKEUP, I2C pins, GPAIN[3:0], RTC_XI, and USB_MXI.

(3) V_DD is the voltage to which the I2C bus pullup resistors are connected.

(4) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(5) When the ANA_LDO supplies V_{DDA_ANA}, it is not recommended to use the GPAIN[3:1] signals for general-purpose outputs (driving high). The I_SD parameter of the ANA_LDO is too low to drive any realistic load on the GPAIN[3:1] pins while also supplying the PLL through V_{DDA_PLL} and the SAR through V_{DDA_ANA}.

(6) I_SD is the amount of current the LDO is ensured to deliver before shutting down to protect itself.

(7) The USB I/Os adhere to the Universal Bus Specification Revision 2.0 (USB2.0 spec).

(8) I_I applies to input-only pins and bidirectional pins. For input-only pins, I_I indicates the input leakage current. For bidirectional pins, I_I indicates the input leakage current and off-state (Hi-Z) output leakage current.

(9) I_OZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

(10) When CV_DD power is "ON", the pin bus-holders are disabled. For more detailed information, see Section 5.7.2.3, Digital I/O Behavior When Core Power (CV_DD) is Down.

(11) This parameter specifies the maximum strength of the Bus Holder and is needed to calculate the minimum strength of external pullups and pulldowns.

5.4 Handling Ratings

		MIN	MAX	UNIT
T_stg	Storage temperature range (default)	–65	150	ºC
Electrostatic Discharge (ESD) Stress Voltage⁽¹⁾	Human Body Model (HBM)⁽²⁾	0	>1000	V
Electrostatic Discharge (ESD) Stress Voltage⁽¹⁾	Charged Device Model (CDM)⁽³⁾	0	>250	V

(1) ESD to measure device sensitivity and immunity to damage caused by electrostatic discharges into the device.

(2) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if the necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.

(3) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

Section 5.5 shows the thermal resistance characteristics for the PBGA–ZCH mechanical package.

5.5 Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)

NO.				°C/W⁽¹⁾	AIR FLOW (m/s)⁽²⁾
1	RT_JC	Junction-to-case	1S0P	6.74	N/A
2	RT_JB	Junction-to-board	1S0P	14.5	N/A
2	RT_JB	Junction-to-board	2S2P	13.8	N/A
3	RT_JA	Junction-to-free air	1S0P	57.0	0.00
3	RT_JA	Junction-to-free air	2S2P	33.4	0.00
4	RT_JMA	Junction-to-moving air			0.50
5					1.00
6					2.00
7					3.00
8	Psi_JT	Junction-to-package top		0.09	0.00
9					0.50
10					1.00
11					2.00
12					3.00
13	Psi_JB	Junction-to-board		13.7	0.00
14					0.50
15					1.00
16					2.00
17					3.00

(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

(2) m/s = meters per second

5.6 Power-On Hours

Over Operating Case Temperature Range (Unless Otherwise Noted)

Device Operating Life Power-On Hours (POH)⁽¹⁾	DSP Operating Frequency (SYSCLK): ≤200 MHz	Commercial	-10 to 70°C	100,000 POH⁽²⁾
		Industrial	-40 to 85°C

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.

(2) POH = 100,000 when the Maximum Core Supply Voltages are limited to 105% of the Nominal Core Supply Voltages (For details on the Core Supplies, see Section 5.2, Recommended Operating Conditions).

5.7 Timing and Switching Characteristics

5.7.1 Parameter Information

Figure 5-1 3.3-V Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

5.7.1.1 1.8-V, 2.75-V, and 3.3-V Signal Transition Levels

All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks, V_OL MAX and V_OH MIN for output clocks.

Figure 5-2 Rise and Fall Transition Time Voltage Reference Levels

5.7.1.2 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

5.7.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routing. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing and decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report [literature number SPRA839]. If needed, external logic hardware such as buffers may be used to compensate any timing differences.

5.7.2 Power Supplies

5.7.2.1 Power Considerations

The device provides several means of managing power consumption.

To minimize power consumption, the device divides its circuits into nine main isolated supply domains:

LDOI (LDOs and Bandgap Power Supply)
Analog POR, SAR, and PLL (V_{DDA_ANA} and V_{DDA_PLL})
RTC Core (CV_DDRTC) — Note: CV_DDRTC must always be powered by an external power source. None of the on-chip LDOs can be used to power CV_DDRTC.
Digital Core (CV_DD)
USB Core (USB_V_DD1P3 and USB_V_DDA1P3)
USB PHY and USB PLL (USB_V_DDOSC, USB_V_DDA3P3, and USB_V_DDPLL)
EMIF I/O (DV_DDEMIF)
RTC I/O (DV_DDRTC)
Rest of the I/O (DV_DDIO)

5.7.2.1.1 LDO Configuration

The device includes three Low-Dropout Regulators (LDOs) which can be used to regulate the power supplies of the SAR ADC and Power Management (ANA_LDO), Digital Core (DSP_LDO), and USB Core (USB_LDO).

These LDOs are controlled by a combination of pin configuration and register settings. For more detailed information see the following sections.

5.7.2.1.1.1 LDO Inputs

The LDOI pins (B12, F13, F14) provide power to the internal Analog LDO, DSP LDO, USB LDO, the bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap provides accurate voltage and current references to the POR, LDOs, PLL, and SAR; therefore, for proper device operation, power must always be applied to the LDOI pins even if the LDO outputs are not used.

5.7.2.1.1.2 LDO Outputs

The ANA_LDOO pin (A12) is the output of the internal ANA_LDO and can provide regulated 1.3 V power of up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the V_{DDA_ANA} pin to provide a regulated 1.3 V to the 10-bit SAR ADC and Power Management Circuits. V_{DDA_ANA} may be powered by this LDO output, which is recommended, to take advantage of the device's power management techniques, or by an external power supply. The ANA_LDO cannot be disabled individually (see Section 5.7.2.1.1.2.1, LDO Control).

The DSP_LDOO pin (E10) is the output of the internal DSP_LDO and provides software-selectable regulated 1.3 V or regulated 1.05 V power of up to 250 mA. The DSP_LDOO pin is intended to be connected, on the board, to the CV_DD pins. In this configuration, the DSP_LDO_EN pin should be tied to the board V_SS, thus enabling the DSP_LDO.

Optionally, the CV_DD pins may be powered by an external power supply. In this configuration the DSP_LDO_EN pin should be tied (high) to LDOI, disabling DSP_LDO.

The DSP_LDO_EN also affects how reset is generated to the chip (for more details, see the DSP_LDO_EN pin description in Table 4-17, Regulators and Power Management Signal Descriptions). When the DSP_LDO is disabled, its output pin is in a high-impedance state.

The LDOs cannot supply power to CV_DDRTC, which requires an external power source because CV_DDRTC must always be on for proper operation.

NOTE

DSP_LDO can only provide a regulated 1.05 V or 1.3 V. When the DSP Core (CV_DD) requires 1.4 V, an external supply is required to supply 1.4 V to the DSP Core (CV_DD) and the DSP_LDO_EN pin should be tied to LDOI.

The USB_LDOO pin (F12) is the output of the internal USB_LDO and provides regulated 1.3 V, software-switchable (on and off) power of up to 25 mA. The USB_LDOO pin is intended to be connected, on the board, to the USB_V_DD1P3 and USB_V_DDA1P3 pins to provide power to portions of the USB. Optionally, the USB_V_DD1P3 and USB_V_DDA1P3 may be powered by an external power supply and the USB_LDO can be left disabled. When the USB_LDO is disabled, its output pin is in a high-impedance state.

5.7.2.1.1.2.1 LDO Control

All three LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the LDO_PD bit in the RTCPMGT register (see Figure 5-3). When the LDOs are disabled via this mechanism, the only way to re-enable them is by cycling power to the CV_DDRTC pin.

ANA_LDO: The ANA_LDO is only disabled by the BG_PD and the LDO_PD mechanism described above. Otherwise, it is always enabled.

DSP_LDO: The DSP_LDO can be statically disabled by the DSP_LDO_EN pin as described in Section 5.7.2.1.1.2, LDO Outputs. The DSP_LDO can also be dynamically enabled and disabled via the BG_PD and the LDO_PD mechanism described above. The DSP_LDO can change its output voltage dynamically by software via the DSP_LDO_V bit in the LDOCNTL register (see Figure 5-4). The DSP_LDO output voltage is set to 1.3 V at reset.

USB_LDO: The reset state of the USB_LDO is dependent on the setting of CLK_SEL pin. If CLK_SEL is high, the USB_LDO is disabled but can be independently and dynamically enabled or disabled by software via the USB_LDO_EN bit in the LDOCNTL register (see Figure 5-4). If CLK_SEL is low, the USB LDO is enabled at reset and can never be disabled. This is to ensure the USB oscillator has power when it is the source of the system clock.

Table 5-3 shows the ON and OFF control of each LDO and its register control bit configurations.

Figure 5-3 RTC Power Management Register (RTCPMGT) [1930h]

15	14	13	12	11	10	9	8
Reserved
R-0

7	6	5	4	3	2	1	0
Reserved			WU_DOUT	WU_DIR	BG_PD	LDO_PD	RTCCLKOUTEN
			R/W-1	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-1 RTCPMGT Register Bit Descriptions

Bit	Name	Description
15:5	Reserved	Reserved. Read-only, writes have no effect.
4	WU_DOUT	Wakeup output, active low, open-drain. 0 = WAKEUP pin driven low. 1 = WAKEUP pin is in high-impedance (Hi-Z).
3	WU_DIR	Wakeup pin direction control. 0 = WAKEUP pin configured as a input. 1 = WAKEUP pin configured as a output. Note: When the WAKEUP pin is configured as an input, it is active high. When the WAKEUP pin is configured as an output, is an open-drain that is active low and should be externally pulled-up via a 10-kΩ resistor to DV_DDRTC. WU_DIR must be configured as an input to allow the WAKEUP pin to wake the device up from idle modes.
2	BG_PD	Bandgap, on-chip LDOs, and the analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO), the Analog POR, and Bandgap reference. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power-down mechanisms should not be used. After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can be re-enabled by the WAKEUP pin (high) or the RTC alarm interrupt. The Bandgap circuit will take about 100 msec to charge the external 0.1 uF capacitor via the internal 326-kΩ resistor. 0 = On-chip LDOs, Analog POR, and Bandgap reference are enabled. 1 = On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).
1	LDO_PD	On-chip LDOs and Analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO) and the Analog POR. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power-down mechanisms should not be used. After this bit is asserted, the on-chip LDOs and Analog POR can be re-enabled by the WAKEUP pin (high) or the RTC alarm interrupt. This bit keeps the Bandgap reference turned on to allow a faster wake-up time with the expense power consumption of the Bandgap reference. 0 = On-chip LDOs and Analog POR are enabled. 1 = On-chip LDOs and Analog POR are disabled (shutdown).
0	RTCCLKOUTEN	Clockout output enable bit. 0 = Clock output disabled. 1 = Clock output enabled.

Figure 5-4 LDO Control Register (LDOCNTL) [7004h]

15	14	13	12	11	10	9	8
Reserved
R-0

7	6	5	4	3	2	1	0
Reserved						DSP_LDO_V	USB_LDO_EN
R-0						R/W-0	R/W-CLK_SEL

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-2 LDOCNTL Register Bit Descriptions

Bit	Name	Description
15:2	Reserved	Reserved. Read-only, writes have no effect.
1	DSP_LDO_V	DSP_LDO voltage select bit. 0 = DSP_LDOO is regulated to 1.3 V. 1 = DSP_LDOO is regulated to 1.05 V.
0	USB_LDO_EN	USB_LDO enable bit. The reset state of this bit is dependent on the setting of CLK_SEL pin at reset. If CLK_SEL is high, the USB_LDO is disabled (USB_LEO_EN = 0). If CLK_SEL is low, the USB LDO is enabled (USB_LDO_EN=1). 0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state. 1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V. Note: When CLK_SEL = 0, this bit will not be able to be set to 0 and the USB_LDO will stay enabled.

Bit

Name

Description

15:2

Reserved

Reserved. Read-only, writes have no effect.

DSP_LDO_V

DSP_LDO voltage select bit.
0 = DSP_LDOO is regulated to 1.3 V.
1 = DSP_LDOO is regulated to 1.05 V.

USB_LDO_EN

USB_LDO enable bit.

The reset state of this bit is dependent on the setting of CLK_SEL pin at reset.

If CLK_SEL is high, the USB_LDO is disabled (USB_LEO_EN = 0).

If CLK_SEL is low, the USB LDO is enabled (USB_LDO_EN=1).

0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state.

1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V.

Note: When CLK_SEL = 0, this bit will not be able to be set to 0 and the USB_LDO will stay enabled.

Table 5-3 LDO Controls Matrix

RTCPMGT Register (0x1930)		LDOCNTL Register (0x7004)	DSP_LDO_EN (Pin D12)	CLK_SEL (Pin C7)	ANA_LDO	DSP_LDO	USB_LDO
BG_PD Bit	LDO_PD Bit	USB_LDO_EN Bit	DSP_LDO_EN (Pin D12)	CLK_SEL (Pin C7)	ANA_LDO	DSP_LDO	USB_LDO
1	Don't Care	Don't Care	Don't Care	0	OFF	OFF	ON
Don't Care	1	Don't Care	Don't Care	0	OFF	OFF	ON
0	0	Don't Care	Low	0	ON	ON	ON
0	0	Don't Care	High	0	ON	OFF	ON
1	Don't Care	Don't Care	Don't Care	1	OFF	OFF	OFF
Don't Care	1	Don't Care	Don't Care	1	OFF	OFF	OFF
0	0	0	Low	1	ON	ON	OFF
0	0	0	High	1	ON	OFF	OFF
0	0	1	Low	1	ON	ON	ON
0	0	1	High	1	ON	OFF	ON

5.7.2.2 Power-Supply Sequencing

The device includes four core voltage-level supplies (CV_DD, CV_DDRTC, USB_V_DD1P3, USB_V_DDA1P3), and several I/O supplies including—DV_DDIO, DV_DDEMIF, DV_DDRTC, USB_V_DDOSC, and USB_V_DDA3P3.

Some TI power-supply devices include features that facilitate power sequencing—for example, Auto-Track and Slow-Start and Enable features. For more information regarding TI's power management products and suggested devices to power TI DSPs, visit www.ti.com/processorpower.

The device does not require a specific power-up sequence. However, if the DSP_LDO is disabled (DSP_LDO_EN = high) and an external regulator supplies power to the CPU Core (CV_DD), the external reset signal (RESET) must be held asserted until all of the supply voltages reach their valid operating ranges.

Note: the external reset signal on the RESET pin must be held low until all of the power supplies reach their operating voltage conditions.

The I/O design allows either the core supplies (CV_DD, CV_DDRTC, USB_V_DD1P3, USB_V_DDA1P3) or the I/O supplies (DV_DDIO, DV_DDEMIF, DV_DDRTC, USB_V_DDOSC, and USB_V_DDA3P3) to be powered up for an indefinite period of time while the other supply is not powered if the following constraints are met:

All maximum ratings and recommended operating conditions are satisfied.
All warnings about exposure to maximum rated and recommended conditions, particularly junction temperature are satisfied. These apply to power transitions as well as normal operation.
Bus contention while core supplies are powered must be limited to 100 hours over the projected lifetime of the device.
Bus contention while core supplies are powered down does not violate the absolute maximum ratings.

If the USB subsystem is used, the subsystem must be powered up in the following sequence:

USB_V_DDA1P3 and USB_V_DD1P3
USB_V_DDA3P3
USB_V_BUS

If the USB subsystem is not used, the following can be powered off:

USB Core
- USB_V_DD1P3
- USB_V_DDA1P3
USB PHY and I/O Level Supplies
- USB_V_DDOSC
- USB_V_DDA3P3
- USB_V_DDPLL

A supply bus is powered up when the voltage is within the recommended operating range. The supply bus is powered down when the voltage is below that range, either stable or while in transition.

5.7.2.3 Digital I/O Behavior When Core Power (CV_DD) is Down

With some exceptions (listed below), all digital I/O pins on the device have special features to allow powering down of the Digital Core Domain (CV_DD) without causing I/O contentions or floating inputs at the pins (see Figure 5-5). The device asserts the internal signal called HHV high when power has been removed from the Digital Core Domain (CV_DD). Asserting the internal HHV signal causes the following conditions to occur in any order:

All output pin strong drivers to go to the high-impedance (Hi-Z) state
Weak bus holders to be enabled to hold the pin at a valid high or low
The internal pullups or pulldowns (IPUs and IPDs) on the I/O pins will be disabled

The exception pins that do not have this special feature are:

Pins driven by the CV_DDRTC Power Domain [This power domain is "Always On"; therefore, the pins driven by CV_DDRTCdo not need these special features]:
- RTC_XI, RTC_XO, RTC_CLKOUT, and WAKEUP
USB Pins:
- USB_DP, USB_DM, USB_R1, USB_VBUS, USB_MXI, and USB_MXO
Pins for the Analog Block:
- GPAIN[3:0], DSP_LDO_EN, and BG_CAP

Figure 5-5 Bus Holder I/O Circuit

NOTE

Figure 5-5 shows both a pullup and pulldown but pins only have one, not both.

PI = Pullup and Pulldown Inhibit

GZ = Output Enable (active low)

HHV = Described in Section 5.7.2.3

5.7.2.4 Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the device, the PC board should include separate power planes for core, I/O, V_{DDA_ANA} and V_{DDA_PLL} (which can share the same PCB power plane), and ground; all bypassed with high–quality low–ESL and ESR capacitors.

5.7.2.5 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place capacitors (caps) as close as possible to the device. These caps need to be no more than 1.25 cm maximum distance from the device power pins to be effective. Physically smaller caps, such as 0402, are better but need to be evaluated from a yield and manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value.

Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 10 µF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint.

As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered.

The recommended decoupling capacitance for the DSP core supplies should be 1 µF in parallel with 0.01-µF capacitor per supply pin.

5.7.2.6 LDO Input Decoupling

The LDO inputs should follow the same decoupling guidelines as other power-supply pins above.

5.7.2.7 LDO Output Decoupling

The LDO circuits implement a voltage feedback control system which has been designed to optimize gain and stability tradeoffs. As such, there are design assumptions for the amount of capacitance on the LDO outputs. For proper device operation, the following external decoupling capacitors should be used when the on-chip LDOs are enabled:

ANA_LDOO– 1µF
DSP_LDOO – 5µF ~ 10µF
USB_LDOO – 1µF ~ 2µF

5.7.3 Reset

The device has two main types of reset: hardware reset and software reset.

Hardware reset is responsible for initializing all key states of the device. The hardware reset occurs whenever the RESET pin is asserted or when the internal power-on-reset (POR) circuit deasserts an internal signal called POWERGOOD. The device's internal POR is a voltage comparator that monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO is enabled externally by the DSP_LDO_EN pin. POWERGOOD is asserted when the DSP_LDOO voltage is above a minimum threshold voltage provided by the bandgap. When the DSP_LDO is disabled (DSP_LDO_EN is high), the internal voltage comparator becomes inactive, and the POWERGOOD signal logic level is immediately set high. The RESET pin and the POWERGOOD signal are internally combined with a logical AND gate to produce an (active low) hardware reset (see Figure 5-6, Power-On Reset Timing Requirements and Figure 5-7, Reset Timing Requirements).

There are two types of software reset: the CPU's software reset instruction and the software control of the peripheral reset signals. For more information on the CPU's software reset instruction, see the C55x CPU 3.0 CPU Reference Guide [literature number: SWPU073]. In all the device documentation, all references to "reset" refer to hardware reset. Any references to software reset will explicitly state software reset.

The device RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC core. This POR monitors the voltage of CV_DDRTC and resets the RTC registers when power is first applied to the RTC core.

5.7.3.1 Power-On Reset (POR) Circuits

The device includes two power-on reset (POR) circuits, one for the RTC (RTC POR) and another for the rest of the chip (MAIN POR).

5.7.3.1.1 RTC Power-On Reset (POR)

The RTC POR ensures that the flip-flops in the CV_DDRTC power domain have an initial state upon powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC time registers need to be initialized with the current time and date when power is first applied.

5.7.3.1.2 Main Power-On Reset (POR)

The device includes an analog power-on reset (POR) circuit that keeps the DSP in reset until specific voltages have reached predetermined levels. When the DSP_LDO is enabled externally by the DSP_LDO_EN pin, the output of the POR circuit, POWERGOOD, is held low until the following conditions are satisfied:

LDOI is powered and the bandgap is active for at least approximately 8 ms
VDD_ANA is powered for at least approximately 4 ms
DSP_LDOO is above a threshold of approximately 950 mV (see the following Note:)

Note: The POR comparator has hysteresis, so the threshold voltage becomes approximately 850 mV after POWERGOOD signal is set high.

Once these conditions are met, the internal POWERGOOD signal is set high. The POWERGOOD signal is internally combined with the RESET pin signal, via an AND-gate, to produce the DSP subsystem's global reset. This global reset is the hardware reset for the whole chip, except the RTC. When the global reset is deasserted (high), the boot sequence starts. For more detailed information on the boot sequence, see Section 6.4.1, Boot Sequence.

When the DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is de-activated and the POWERGOOD signal is immediately set high. The RESET pin will be the sole source of hardware reset.

5.7.3.1.3 Reset Pin (RESET)

The device can receive an external reset signal on the RESET pin. As specified above in Section 5.7.3.1.2, Main Power-On Reset, the RESET pin is combined with the internal POWERGOOD signal, that is generated by the MAIN POR, via an AND-gate. The output of the AND gate provides the hardware reset to the chip. The RESET pin may be tied high and the MAIN POR can provide the hardware reset in case DSP_LDO is enabled (DSP_LDO_EN = 0), but an external hardware reset must be provided via the RESET pin when the DSP_LDO is disabled (DSP_LDO_EN = 1).

Once the hardware reset is applied, the system clock generator is enabled and the DSP starts the boot sequence. For more information on the boot sequence, see Section 6.4.1, Boot Sequence.

5.7.3.2 Pin Behavior at Reset

All pins are in Hi-Z state when RESET is applied, and pins are held in Hi-Z state for the first two clock cycles after RESET is de-asserted (set to high).

During normal operation, pins are controlled by the respective peripheral selected in the External Bus Selection Register (EBSR) register. During power-on reset and reset, the behavior of the output pins changes and is categorized as follows:

	Z, High Group:EM_CS2, EM_CS3, EM_CS4, EM_CS5, EM_DQM0/UHPI_HBE0, EM_DQM1/UHPI_HBE1, EM_OE, EM_SDCAS/UHPI_HCS, EM_SDRAS/UHPI_HAS, EM_WE, XF
	Z, Low Group: SPI_CLK/UHPI_HINT, I2S2_DX/UHPI_HD[11]/GP[27]/SPI_TX, EM_R/W, MMC0_CLK/I2S0_CLK/GP[0]/McBSP_CLKX, MMC1_CLK/McSPI_CLK/GP[6], EM_SDCLK
	Z Group: EM_D[0:15], GP[21:26]/EM_A[15:20], GP[12:17]/UHPI_HD[2:7], EM_WAIT2, EM_WAIT3, EM_WAIT4, EM_WAIT5, EMU0, EMU1, SCL, SDA, TDO, USB_MXO, WAKEUP, RTC_CLKOUT
	I2S2_CLK/UHPI_HD[8]/GP[18]/SPI_CLK, I2S2_FS/UHPI_HD[9]/GP[19]/SPI_CS0, I2S2_RX/UHPI_HD[10]/GP[20]/SPI_RX
	MMC0_CMD/I2S0_FS/GP[1]/McBSP_FSX, MMC0_D0/I2S0_DX/GP[2]/McBSP_DX, MMC0_D1/I2S0_RX/GP[3]/McBSP_DR, MMC0_D2/GP[4]/McBSP_FSR, MMC0_D3/GP[5]/McBSP_CLKR_CLKS
	MMC1_CMD/McSPI_CS0/GP[7], MMC1_D0/McSPI_SIMO/GP[8], MMC1_D1/McSPI_SOMI/GP[9], MMC1_D2/McSPI_CS1/GP[10], MMC1_D3/McSPI_CS2/GP[11]
	UART_CTS/UHPI_HD[13]/GP[29]/I2S3_FS, UART_RXD/UHPI_HD[14]/GP[30]/I2S3_RX, SPI_TX/UHPI_HD[1], SPI_RX/UHPI_HD[0]
	Z, CLKOUT Group: CLKOUT
	Z Group - Analog: GPAIN0, GPAIN1, GPAIN2, GPAIN3
	Z, SYNCH 0→1 Group: EM_SDCKE/UHPI_HHWIL
	Z, SYNCH 1→0 Group:EM_CS0/UHPI_HDS1, EM_CS1/UHPI_HDS2
	Z, SYNCH22 0→1 Group: SPI_CS0/UHPI_HCNTL0, SPI_CS1/UHPI_HCNTL1, SPI_CS2/UHPI_HR_NW, SPI_CS3/UHPI_HRDY
	Z, SYNCH X→1 Group:EM_BA[0], EM_BA[1], UART_RTS/UHPI_HD[12]/GP[28]/I2S3_CLK, UART_TXD/UHPI_HD[15]/GP[31]/I2S3_DX
	Z, SYNCH X→0 Group: EM_A[0:10], EM_A[11]/(ALE), EM_A[12]/(CLE), EM_A[13], EM_A[14]

5.7.3.3 Reset Electrical Data and Timing

Table 5-4 Timing Requirements for Reset⁽¹⁾ (see Figure 5-6 and Figure 5-7)

NO.			CV_DD = 1.05 V		CV_DD = 1.3/1.4 V		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
1	t_w(RSTL)	Pulse duration, RESET low	3P		3P		ns

(1) P = 1/SYSCLK clock frequency in ns. For example, if SYSCLK = 12 MHz, use P = 83.3 ns. In IDLE3 mode the system clock generator is bypassed and the SYSCLK frequency is equal to either CLKIN or the RTC clock frequency depending on CLK_SEL.
For a description of IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number SPRUH16].

Figure 5-6 Reset Timing When DSP_LDO_EN = 0

Figure 5-7 Reset Timing When DSP_LDO_EN = 1

5.7.3.4 Configurations at Reset

Some device configurations are determined at reset. The following subsections give more details.

5.7.3.4.1 Device and Peripheral Configurations at Device Reset

Table 5-5 summarizes the device boot and configuration pins that are required to be statically tied high, tied low, or left unconnected during device operation. For proper device operation, a device reset should be initiated after changing any of these pin functions.

Table 5-5 Default Functions Affected by Device Configuration Pins

CONFIGURATION PINS	SIGNAL NO.	IPU and IPD	FUNCTIONAL DESCRIPTION
DSP_LDO_EN	D12	–	DSP_LDO enable input. This signal is not intended to be dynamically switched. 0 = DSP_LDO is enabled. The internal DSP LDO is enabled to regulate power on the DSP_LDOO pin at either 1.3 V or 1.05 V according to the LDO_DSP_V bit in the LDOCNTL register, see Figure 5-4). At power-on-reset, the internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO voltage is above a minimum threshold voltage. The internal device reset is generated by the AND of POWERGOOD and the RESET pin. 1 = DSP_LDO is disabled and the DSP_LDOO pin is in high-impedance (Hi-Z). The internal voltage monitoring on the DSP_LDOO is bypassed and the internal POWERGOOD signal is immediately set high. The RESET pin (D6) will act as the sole reset source for the device. If an external power supply is used to provide power to CV_DD, then DSP_LDO_EN should be tied to LDOI, DSP_LDOO should be left unconnected, and the RESET pin must be asserted appropriately for device initialization after powerup. Note: to pullup this pin, connect it to the same supply as LDOI pins.
CLK_SEL	C7	–	Clock input select. 0 = The on-chip USB oscillator is enabled and drives the system clock generator. Also, the USB LDOO is enabled at reset (USB_LDO_EN=1). In this configuration, CLKIN must be tied to GND. 1 = CLKIN drives the system clock generator. The on-chip USB oscillator and USB_LDO are disabled at reset (USB_LDO_EN=0) but can be enabled by software This pin is not allowed to change during device operation; it must be tied to DV_DDIO or GND at the board.

CONFIGURATION PINS

SIGNAL NO.

IPU and IPD

FUNCTIONAL DESCRIPTION

DSP_LDO_EN

D12

–

DSP_LDO enable input.
This signal is not intended to be dynamically switched.
0 = DSP_LDO is enabled. The internal DSP LDO is enabled to regulate power on the DSP_LDOO pin at either 1.3 V or 1.05 V according to the LDO_DSP_V bit in the LDOCNTL register, see Figure 5-4). At power-on-reset, the internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO voltage is above a minimum threshold voltage. The internal device reset is generated by the AND of POWERGOOD and the RESET pin.
1 = DSP_LDO is disabled and the DSP_LDOO pin is in high-impedance (Hi-Z). The internal voltage monitoring on the DSP_LDOO is bypassed and the internal POWERGOOD signal is immediately set high. The RESET pin (D6) will act as the sole reset source for the device. If an external power supply is used to provide power to CV_DD, then DSP_LDO_EN should be tied to LDOI, DSP_LDOO should be left unconnected, and the RESET pin must be asserted appropriately for device initialization after powerup.

Note: to pullup this pin, connect it to the same supply as LDOI pins.

CLK_SEL

–

Clock input select.

0 = The on-chip USB oscillator is enabled and drives the system clock generator. Also, the USB LDOO is enabled at reset (USB_LDO_EN=1). In this configuration, CLKIN must be tied to GND.

1 = CLKIN drives the system clock generator. The on-chip USB oscillator and USB_LDO are disabled at reset (USB_LDO_EN=0) but can be enabled by software

This pin is not allowed to change during device operation; it must be tied to DV_DDIO or GND at the board.

For proper device operation, external pullup and pulldown resistors may be required on these device configuration pins. For discussion on situations where external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.

This device also has RESERVED pins that need to be configured correctly for proper device operation (statically tied high, tied low, or left unconnected at all times). For more details on these pins, see Table 4-24, Reserved and No Connects Signal Descriptions.

5.7.3.4.2 BootMode Implementation and Requirements

The EM_A[20:15]/GP[26:21] pins are used to latch the bootmode, as defined in Table 6-34. These pins are defined as GPIO function at reset and they are in input state. Therefore these pins can be driven to the desired bootmode terminations at reset. Approximately 10 system cycles after the rising edge of the RESET pin, the state on these pins will be latched into registers readable by the DSP at IO-space address 0x1C5A.

As the bootloader code starts executing, it reads the latched value in the bootmode register and uses that value to determine from which peripheral or method to boot. In any case where the ASYNC modes (except for NAND) are used as the source data for bootloading (for example, bootload from external NOR flash to internal memory), the bootloader routine in ROM will change the EM_A[20:15] or GP[26:21] pins from GPIO mode to EMIF mode by writing to the EBSR (0x1C00). When this occurs, no signal contentions must be on the EM_A[20:15] or GP[26:21] pins. Passive static terminations by external pullup or pulldown resistors should also be considered.

Note: Bootloading directly to external peripherals on the EMIF is not supported because the EMIF clock is turned off before jumping to bootloaded code.

The bootloader must enable the EMIF function on these pins in order to increase the address reach from 15-bits (EM_A[14:0] 32 kW) to the full 21-bits (EM_A[20:0] 2 MW). The bootloader does not have to enable the EMIF mode on the EM_A[20:15] or GP[26:21] pins for the following external memory types:

NAND: Uses the EM_D[15:0] pins for both address and data and command signaling.

SDRAM: Uses column and row addressing using no more than 11 bits of EM_A pins

The following image contains two BootMode termination scenarios. Other options are also possible.

Figure 5-8 BootMode Termination Scenarios

A. DSP changes the pin mode to EMIF Address (outputs) only if needed for the selected bootmode.

Figure 5-9 BootMode Latching

5.7.3.5 Configurations After Reset

The following sections provide details on configuring the device after reset. Multiplexed pin functions are selected by software after reset. For more details on multiplexed pin function control, see Section 4.3, Pin Multiplexing.

5.7.3.5.1 External Bus Selection Register (EBSR)

The External Bus Selection Register (EBSR) determines the mapping of the UHPI, I2S2, I2S3, UART, SPI, McBSP, McSPI, and GPIO signals to 28 signals of the external parallel port pins. The EBSR also determines the mapping of the I2S, McBSP, McSPI, GPIO, or MMC and SD ports to serial port 0 pins and serial port 1 pins. The EBSR register is located at IO-space 0x1C00. Once the bit fields of this register are changed, the routing of the signals takes place on the next CPU clock cycle.

In addition, the EBSR controls the function of the upper bits of the EMIF address bus. Pins EM_A[20:15] or GP[26:21] can be individually configured as GPIO pins through the Axx_MODE bits. When Axx_MODE = 1, the EM_A[xx] pin functions as a GPIO pin. When Axx_MODE = 0, the EM_A[xx] pin has EMIF address output functionality.

Before modifying the values of the external bus selection register, you must clock gate all affected peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register has been modified, you must reset the peripherals before using them through the Peripheral Software Reset Counter Register.

Figure 5-10 External Bus Selection Register (EBSR) [1C00h]

15	14	13	12	11	10	9	8
McBSP_CLKS Selection	PPMODE			SP1MODE		SP0MODE
R/W-0	R/W-001			R/W-00		R/W-00

7	6	5	4	3	2	1	0
Reserved		A20_MODE	A19_MODE	A18_MODE	A17_MODE	A16_MODE	A15_MODE
R-0		R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-6 EBSR Register Field Descriptions

Bit	Field	Description
		McBSP_CLKS Selection
15	McBSP_CLKS Selection	0 = McBSP_CLKR signal is routed to MMC0_D3/GP[5]/McBSPCLKR_CLKS (L11) when SP0MODE=3
		1 = McBSP_CLKS signal is routed to MMC0_D3/GP[5]/McBSPCLKR_CLKS (L11) when SP0MODE=3
14:12	PPMODE	Parallel Port Mode Control Bits. These bits control the pin multiplexing of the UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] pins on the parallel port. For more details, see Table 4-20. 000 = Mode 0 (16-bit UHPI bus). All 28 signals of the UHPI bus module are routed to the 28 external signals of the parallel port. Note: SDRAM control signals are multiplexed with UHPI bus control signals. In this mode, UHPI bus signals are routed to the control ports, so SDRAM cannot be accessible. 001 = Mode 1 (SPI, GPIO, UART, I2S2, and SDRAM). 7 signals of the SPI module, 6 GPIO signals, 4 signals of the UART module, 4 signals of the I2S2 module, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port. 010 = Mode 2 (GPIO and SDRAM). 8 GPIO and 7 SDRAM control signals are routed to the 28 external signals of the parallel port. 011 = Mode 3 (SPI, I2S3, and SDRAM). 4 signals of the SPI module, 4 signals of the I2S3 module, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port. 100 = Mode 4 (I2S2, UART, and SDRAM). 4 signals of the I2S2 module, 4 signals of the UART module, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port. 101 = Mode 5 (SPI, UART, and SDRAM). 4 signals of the SPI module, 4 signals of the UART module, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port. 110 = Mode 6 (SPI, I2S2, I2S3, GPIO, and SDRAM). 7 signals of the SPI module, 4 signals of the I2S2 module, 4 signals of the I2S3 module, 6 GPIO, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port. 111 = Reserved.
11:10	SP1MODE	Serial Port 1 Mode Control Bits. The bits control the pin multiplexing of the MMC1, McSPI, and GPIO pins on serial port 1. For more details, see Table 4-21. 00 = Mode 0 (MMC1 and SD1). All 6 signals of the MMC1 and SD1 module are routed to the 6 external signals of the serial port 1. 01 = Mode 1 (McSPI). 6 signals of the McSPI module signals are routed to the 6 external signals of the serial port 1. 10 = Mode 2 (GP[11:6]). 6 GPIO signals (GP[11:6]) are routed to the 6 external signals of the serial port 1. 11 = Reserved.
9:8	SP0MODE	Serial Port 0 Mode Control Bits. The bits control the pin multiplexing of the MMC0, I2S0, McBSP, and GPIO pins on serial port 0. For more details, see Section 4.3.3. 00 = Mode 0 (MMC0 and SD0). All 6 signals of the MMC0 and SD0 module are routed to the 6 external signals of the serial port 0. 01 = Mode 1 (I2S0 and GP[5:4]). 4 signals of the I2S0 module and 2 GP[5:4] signals are routed to the 6 external signals of the serial port 0. 10 = Mode 2 (GP[5:0]). 6 GPIO signals (GP[5:0]) are routed to the 6 external signals of the serial port 0. 11 = Mode 3 (McBSP). 6 signals of the McBSP module are routed to the 6 external signal port 0.
7-6	Reserved	Reserved. Read-only, writes have no effect.
5	A20_MODE	A20 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 20 (EM_A[20]) and general-purpose input/output pin 26 (GP[26]) pin functions. 0 = Pin function is EMIF address pin 20 (EM_A[20]). 1 = Pin function is general-purpose input/output pin 26 (GP[26]). This is the default mode at reset and the pin is configured as an Input. Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the BootMode register to specify the boot method.
4	A19_MODE	A19 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 19 (EM_A[19]) and general-purpose input/output pin 25 (GP[25]) pin functions. 0 = Pin function is EMIF address pin 19 (EM_A[19]). 1 = Pin function is general-purpose input/output pin 25 (GP[25]). This is the default mode at reset and the pin is configured as an Input. Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the BootMode register to specify the boot method.
3	A18_MODE	A18 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 18 (EM_A[18]) and general-purpose input/output pin 24 (GP[24]) pin functions. 0 = Pin function is EMIF address pin 18 (EM_A[18]). 1 = Pin function is general-purpose input/output pin 24 (GP[24]). This is the default mode at reset and the pin is configured as an Input. Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the BootMode register to specify the boot method.
2	A17_MODE	A17 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 17 (EM_A[17]) and general-purpose input/output pin 23 (GP[23]) pin functions. For more details, see Table 4-22, MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing. 0 = Pin function is EMIF address pin 17 (EM_A[17]). 1 = Pin function is general-purpose input/output pin 23 (GP[23]). This is the default mode at reset and the pin is configured as an Input. Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the BootMode register to specify the boot method.
1	A16_MODE	A16 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 16 (EM_A[16]) and general-purpose input/output pin 22 (GP[22]) pin functions. For more details, see Table 4-22, MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing. 0 = Pin function is EMIF address pin 16 (EM_A[16]). 1 = Pin function is general-purpose input/output pin 22 (GP[22]). This is the default mode at reset and the pin is configured as an Input. Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the BootMode register to specify the boot method.
0	A15_MODE	A15 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 15 (EM_A[15]) and general-purpose input/output pin 21 (GP[21]) pin functions. For more details, see Table 4-22, MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing. 0 = Pin function is EMIF address pin 15 (EM_A[15]). 1 = Pin function is general-purpose input/output pin 21 (GP[21]). This is the default mode at reset and the pin is configured as an Input. Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the BootMode register to specify the boot method.

5.7.3.5.2 LDO Control Register [7004h]

When the DSP_LDO is enabled by the DSP_LDO_EN pin being tied low, the DSP_LDOO voltage is set by the DSP_LDO_V bit in this register. The reset state of this bit causes the DSP_LDOO output to be set to 1.3 V at boot. The DSP_LDOO voltage can be programmed to be either 1.05 V or 1.3 V via the DSP_LDO_V bit (bit 1) in the LDO Control Register (LDOCNTL).

At reset, the USB_LDO state is dependent on the CLK_SEL pin. At reset, if CLK_SEL is high (CLK_SEL=1), the USB LDO is disabled but can be enabled via the USBLDOEN bit (bit 0) in the LDOCNTL register. If CLK_SEL is low (CLK_SEL=0), the USB LDO is enabled and cannot be disabled.

For more detailed information on the LDOs, see Section 5.7.2.1.1, LDO Configuration.

5.7.3.5.3 EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h]

After reset, by default, the CPU performs 16-bit accesses to the EMIF and USB registers and data space. To perform 8-bit accesses to the EMIF data space, the user must set the BYTEMODE bits to 01b for the "high byte" or 10b for the "low byte" in the EMIF System Control Register (ESCR). Similarly, the BYTEMODE bits in the USB System Control Register (USBSCR) must also be configured for byte access.

5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]

After hardware reset, the DSP executes the on-chip bootloader from ROM. Depending on the BootMode used, the bootloader may leave the PCGCR1 and the PCGCR2 registers in various states. This is also true of the ICR and the ISR registers.

Programmers should always verify the state of these registers and appropriately set them. Their states after boot loading are not determined by their reset conditions.

5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PUDINHIBR1, 2, 3, 4, 5, 6, and 7) [1C17h, 1C18h, 1C19h, 1C4Ch, 1C4Dh, 1C4Fh, and 1C50h, respectively]

Each internal pullup and pulldown (IPU and IPD) resistor on the device can be individually controlled through the IPU and IPD registers (PUDINHIBR1 [1C17h] , PUDINHIBR2 [1C18h], PUDINHIBR3 [1C19h], PUDINHIBR4 [1C4Ch], PUDINHIBR5 [1C4Dh], PUDINHIBR6 [1C4Fh], and PUDINHIBR7 [1C50h]). To minimize power consumption, internal pullup or pulldown resistors should be disabled in the presence of an external pullup or pulldown resistor or external driver. Most internal pullups and pulldowns are enabled at reset to help ensure no pins are left floating. Section 5.7.20.1.1, Pullup and Pulldown Resistors, describes other situations in which an pullup and pulldown resistors are required.

When CV_DD is powered down, pullup and pulldown resistors will be forced disabled and an internal bus-holder will be enabled. For more detailed information, see Section 5.7.2.3, Digital I/O Behavior When Core Power (CV_DD) is Down.

5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]

To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIF and CLKOUT output pins. The output slew rate control register (OSRCR) is used to set a subset of the device I/O pins, namely CLKOUT and EMIF pins, to either fast or slow slew rate. The slew rate feature is implemented by staging and delaying turn-on times of the parallel p-channel drive transistors and parallel n-channel drive transistors of the output buffer. In the slow slew rate configuration, the delay is longer, but ultimately the same number of parallel transistors are used to drive the output high or low. Thus, the drive strength is ultimately the same. The slower slew rate control can be used for power savings and has the greatest effect at lower DV_DDIO and DV_DDEMIF voltages.

5.7.4 Clock Specifications

5.7.4.1 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic manner.

5.7.4.2 Clock Considerations

The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system clock generator. The system clock generator features a software-programmable PLL multiplier and several dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of the on-chip USB oscillator. The selection of the input reference clock is based on the state of the CLK_SEL pin. The CLK_SEL pin is required to be statically tied high or low and cannot change dynamically after reset.

If CLK_SEL=0 at reset, the on-chip USB oscillator is selected as the source of the system clock generator and the USB PLL as well. In this configuration, the on-chip USB oscillator cannot be turned off.

If CLK_SEL=1 at reset, the external clock via the CLKIN pin will be used as the source of the system clock generator and the on-chip USB oscillator is used only for the USB PLL input. In this configuration, the on-chip USB oscillator can be turned off if the USB peripheral is not being used.

In addition, the DSP requires a reference clock for the real-time clock (RTC). The RTC reference clock is generated using a dedicated on-chip oscillator with a 32.768-kHz external crystal connected to the RTC_XI and RTC_XO pins.

The 32.768-kHz crystal can be disabled if the RTC peripheral is not being used. However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers (I/O address range 1900h – 197Fh) will not be accessible. This includes the RTC power management register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator, connect the RTC_XI pin to CV_DDRTC and the RTC_XO pin to ground.

For more information on crystal specifications for the RTC oscillator and the USB oscillator, see Section 5.7.4.3.3, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins.

5.7.4.2.1 Clock Configurations After Device Reset

After reset, the on-chip Bootloader programs the system clock generator based on the value of EM_A[20:15] or GP[26:21], which are latched into the BootMode[5:0] bits in the BootMode register ([1C34h]) at reset. (See Section 6.4, Boot Modes, for details.)

5.7.4.2.1.1 Device Clock Frequency

After the boot process is complete, the user is allowed to re-program the system clock generator to bring the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not). The user must adhere to various clock requirements when programming the system clock generator. For more information, see Section 5.7.4.3, Clock PLLs.

Note: The on-chip Bootloader allows for DSP registers to be configured during the boot process. However, this feature must not be used to change the output frequency of the system clock generator during the boot process. The bootloader also uses Timer0 to calculate the settling time of BG_CAP until executing bootloader code. The bootloader register modification feature must not modify the Timer0 registers.

5.7.4.2.1.2 Peripheral Clock State

The clock and reset state of each of peripheral is controlled through a set of system registers. The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control register (PRCR) are used to assert and de-assert peripheral reset signals.

After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the bootloader chooses a peripheral or method to boot from based on the value of BootMode[5:0] bits in the BootMode register ([1C34h]) and queries the peripheral to determine if it can boot from that peripheral. At that time, the individual peripheral clock will be enabled for the query and then disabled again when the bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be idled.

5.7.4.2.1.3 USB Oscillator Control

At reset, if CLK_SEL = 0, the on-chip USB oscillator is enabled and is used as the clock source of the system clock generator. Since the USB oscillator is the system's clock source, it is not possible to disable the USB oscillator when CLK_SEL = 0.

When CLK_SEL = 1, the USB Oscillator is disabled at reset but can be enabled or disabled by writing to the USB system control register (USBSCR). To enable the oscillator, the USBOSCDIS and USBOSCBIASDIS bits must be cleared to 0. The user must wait until the USB oscillator stabilizes before proceeding with the USB configuration. The USB oscillator stabilization time is typically 100 µs, with a 10 ms maximum. (Note: The startup time is highly dependent on the ESR and capacitive load on the crystal.)

5.7.4.3 PLLs

The device DSP uses a software-programmable PLL to generate frequencies required by the CPU, DMA, and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the USB on-chip oscillator (as specified through the CLK_SEL pin).

5.7.4.3.1 PLL Device-Specific Information

There is a minimum and maximum operating frequency for CLKIN, PLLIN, and the system clock (SYSCLK). The system clock generator must be configured not to exceed any of these constraints documented in this section (certain combinations of external clock inputs, internal dividers, and PLL multiply ratios are not supported).

Table 5-7 PLL Clock Frequency Ranges

CLOCK SIGNAL NAME	CV_DD = 1.05 V V_{DDA_PLL} = 1.3 V			CV_DD = 1.3 V V_{DDA_PLL} = 1.3 V			CV_DD = 1.4 V V_{DDA_PLL} = 1.3 V			UNIT
CLOCK SIGNAL NAME	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
CLKIN⁽¹⁾		11.2896, 12.0, 12.288, 16.8, or 19.2			11.2896, 12.0, 12.288, 16.8, or 19.2			11.2896, 12.0, 12.288, 16.8, or 19.2		MHz
PLLIN	1.7		6.79	1.7		6.79	1.7		6.79	MHz
PLLOUT	60		120	60		120	60		120
VCO Output⁽²⁾ (before output divider OD and OD2)	125		625	125		625	125		625	MHz
SYSCLK	0		75	0		175	0		200	MHz
PLL_LOCKTIME			4			4			4	ms

(1) These CLKIN values are used when the CLK_SEL pin = 1.

(2) To use less PLL power, ensure VCO max is close to the SYSCLK max.

The PLL has lock time requirements that must be followed. The PLL lock time is the amount of time needed for the PLL to complete its phase-locking sequence.

5.7.4.3.2 Clock PLL Considerations With External Clock Sources

If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single clean power supply should power both the device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.

Rise and fall times, duty cycles (high and low pulse durations), and the load capacitance of the external clock source must meet the device requirements in this data manual (see Section 5.3.2, Electrical Characteristics, and Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.

5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins

The device DSP includes two options to provide an external clock input to the system clock generator:

Use the on-chip USB oscillator with an external 12-MHz crystal connected to the USB_MXO and USB_MXI pins.
Use an external LVCMOS clock input fed into the CLKIN pin that operates at the same voltage as the DV_DDIO supply (1.8-, 2.75-, or 3.3-V).

The CLK_SEL pin determines which input is used as the clock source for the system clock generator. For more details, see Section 5.7.3.4.1.

If CLK_SEL = 0 at reset, the on-chip USB oscillator is used as the source of the system clock generator and the USB PLL as well.

If CLK_SEL= 1 at reset, the external LVCMOS clock input fed into the CLKIN pin will be used as the source of the system clock generator and the on-chip USB oscillator is used only for the USB PLL source. In this configuration, the on-chip USB oscillator can be turned off if the USB peripheral is not being used.

Additionally, the DSP requires a reference clock for the on-chip real time clock (RTC). The RTC reference clock is generated using a dedicated on-chip oscillator with a 32.768-kHz external crystal connected to the RTC_XI and RTC_XO pins. The crystal for the RTC oscillator is not required if the RTC is not used, however the RTC must still be powered by an external power source. None of the on-chip LDOs can power CV_DDRTC. The RTC registers starting at I/O address 1900h will not be accessible without an RTC clock. This includes the RTC Power Management Register which provides control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins. Section 5.7.4.3.3.2, Real-Time Clock (RTC) On-Chip Oscillator With External Crystal, provides more details on using the RTC on-chip oscillator with an external crystal.

5.7.4.3.3.1 USB On-Chip Oscillator With External Crystal

The USB on-chip oscillator requires an external 12-MHz crystal connected across the USB_MXI and USB_MXO pins, along with two load capacitors, as shown in Figure 5-11. The external crystal load capacitors must be connected only to the USB oscillator ground pin (USB_V_SSOSC). Do not connect to board ground (V_SS). The USB_V_DDOSC pin can be connected to the same power supply as USB_V_DDA3P3.

If the external clock input via the CLKIN pin is used as the source of the system clock generator (CLK_SEL =1 at reset) and the USB peripheral is not being used, then the on-chip USB oscillator can be permanently disabled. To permanently disable the USB oscillator, connect the USB_MXI pin to ground (V_SS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_V_DDOSC and USB_V_SSOSC) should also be connected to ground, as shown in Figure 5-12.

When using an external 12-MHz oscillator, the external oscillator clock signal should be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the V_IH requirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO is left unconnected and the USB_V_SSOSC signal is connected to board ground (V_SS).

Figure 5-11 12-MHz USB Oscillator

Figure 5-12 Connections when USB Oscillator is Permanently Disabled

The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series resistance (ESR) specified in Table 5-8. The load capacitors, C1 and C2 are the total capacitance of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal manufacturer's datasheet and should be chosen such that the equation below is satisfied. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (USB_MXI and USB_MXO) and to the USB_V_SSOSC pin.

Table 5-8 Input Requirements for Crystal on the 12-MHz USB Oscillator

PARAMETER	NOM	MAX	UNIT
Start-up time (from power up until oscillating at stable frequency of 12 MHz)⁽²⁾	0.100	10	ms
Oscillation frequency	12		MHz
ESR		100	kΩ
Frequency stability ⁽¹⁾		±100	ppm
Maximum shunt capacitance		5	pF
Maximum crystal drive		330	µW

(1) If the USB is used, a 12-MHz, ±100-ppm crystal is recommended.

(2) The startup time is highly dependent on the ESR and the capacitive load of the crystal.

5.7.4.3.3.2 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal

The on-chip RTC oscillator requires an external 32.768-kHz crystal connected across the RTC_XI and RTC_XO pins, along with two load capacitors, as shown in Figure 5-13. The external crystal load capacitors must be connected only to the RTC oscillator ground pin (V_SSRTC). Do not connect to board ground (V_SS). Position the V_SS lead on the board between RTC_XI and RTC_XO as a shield to reduce direct capacitance between RTC_XI and RTC_XO leads on the board. The CV_DDRTC pin can be connected to the same power supply as CV_DD, or may be connected to a different supply that meets the recommended operating conditions (see Section 5.2, Recommended Operating Conditions), if desired.

Figure 5-13 32.768-kHz RTC Oscillator

The RTC oscillator can be optionally disabled by connecting RTC_XI to CV_DDRTC and RTC_XO to ground (V_SS). However, when the RTC oscillator is disabled the RTC registers starting at I/O address 1900h will not be accessible. This includes the RTC Power Management Register which provides control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins. Note: The RTC must still be powered even if the RTC oscillator is disabled.

Figure 5-14 Connections when RTC Oscillator is Permanently Disabled

The crystal should be in fundamental-mode function, and parallel resonant, with a maximum effective series resistance (ESR) specified in Table 5-9. The load capacitors, C1 and C2, are the total capacitance of the circuit board and components, excluding the IC and crystal. The load capacitors values are usually approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal manufacturer's datasheet and should be chosen such that the equation is satisfied. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (RTC_XI and RTC_XO) and to the V_SSRTC pin.

Table 5-9 Input Requirements for Crystal on the 32.768-kHz RTC Oscillator

PARAMETER	MIN	NOM	MAX	UNIT
Start-up time (from power up until oscillating at stable frequency of 32.768-kHz)⁽¹⁾	0.2		2	sec
Oscillation frequency		32.768		kHz
ESR			100	kΩ
Maximum shunt capacitance			1.6	pF
Maximum crystal drive			1.0	µW

(1) The startup time is highly dependent on the ESR and the capacitive load of the crystal.

5.7.4.3.3.3 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)

Note: If CLKIN is not used, the pin must be tied low.

A LVCMOS-compatible clock can be fed into the CLKIN pin for use by the DSP system clock generator. The external connections are shown in Figure 5-15 and Figure 5-16. The bootloader assumes that the CLKIN pin is connected to the LVCMOS-compatible clock source with a frequency of 11.2896, 12.0, 12.288, 16.8, or 19.2 MHz based on the value of BootMode[5:4] bits at reset. (See Section 6.4, Boot Mode, for details.) Note: The CLKIN pin operates at the same voltage as the DV_DDIO supply (1.8, 2.75, or 3.3 V).

In this configuration the RTC oscillator can be optionally disabled by connecting RTC_XI to CV_DDRTC and RTC_XO to ground (V_SS). However, when the RTC oscillator is disabled the RTC registers starting at I/O address 1900h will not be accessible. This includes the RTC Power Management Register which provides control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins. Note: The RTC must still be powered by an external power source even if the RTC oscillator is disabled. None of the on-chip LDOs can power CV_DDRTC.

Figure 5-15 LVCMOS-Compatible Clock Input With USB Oscillator Enabled

Figure 5-16 LVCMOS-Compatible Clock Input With USB Oscillator Disabled

5.7.4.4 Input and Output Clocks Electrical Data and Timing

Table 5-10 Timing Requirements for CLKIN⁽¹⁾⁽²⁾ (see Figure 5-17)

NO.			CV_DD = 1.05/1.3/1.4 V			UNIT
NO.			MIN	NOM	MAX	UNIT
1	t_c(CLKIN)	Cycle time, external clock driven on CLKIN		11.2896 12.0, 12.288, 16.8, or 19.2		MHz
2	t_w(CLKINH)	Pulse duration, CLKIN high	0.466 * t_c(CLKIN)			ns
3	t_w(CLKINL)	Pulse duration, CLKIN low	0.466 * t_c(CLKIN)			ns
4	t_t(CLKIN)	Transition time, CLKIN			4	ns

(1) The CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for CPU operating frequency.

(2) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.

Figure 5-17 CLKIN Timing

Table 5-11 Switching Characteristics Over Recommended Operating Conditions for CLKOUT
[I/O = 3.3/2.75 V]⁽¹⁾⁽²⁾
(see Figure 5-18)

NO.	PARAMETER		CV_DD = 1.05/1.3/1.4 V V_{DDA_PLL} = 1.3 V		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
1	t_c(CLKOUT)	Cycle time, CLKOUT	10		ns
2	t_w(CLKOUTH)	Pulse duration, CLKOUT high	0.466 * t_c(CLKOUT)		ns
3	t_w(CLKOUTL)	Pulse duration, CLKOUT low	0.466 * t_c(CLKOUT)		ns
4	t_t(CLKOUTR)	Transition time (rise), CLKOUT		5	ns
5	t_t(CLKOUTF)	Transition time (fall), CLKOUT		5	ns

(1) The reference points for the rise and fall transitions are measured at V_OL MAX and V_OH MIN.

(2) P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.

Table 5-12 Switching Characteristics Over Recommended Operating Conditions for CLKOUT
[I/O = 1.8 V]⁽¹⁾⁽²⁾
(see Figure 5-18)

NO.	PARAMETER		CV_DD = 1.05/1.3/1.4 V V_{DDA_PLL} = 1.3 V		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
1	t_c(CLKOUT)	Cycle time, CLKOUT	20		ns
2	t_w(CLKOUTH)	Pulse duration, CLKOUT high	0.466 * t_c(CLKOUT)		ns
3	t_w(CLKOUTL)	Pulse duration, CLKOUT low	0.466 * t_c(CLKOUT)		ns
4	t_t(CLKOUTR)	Transition time (rise), CLKOUT		5	ns
5	t_t(CLKOUTF)	Transition time (fall), CLKOUT		5	ns

(1) The reference points for the rise and fall transitions are measured at V_OL MAX and V_OH MIN.

(2) P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.

Figure 5-18 CLKOUT Timing

5.7.4.5 Wake-up Events, Interrupts, and XF

The device has a number of interrupts to service the needs of its peripherals. The interrupts can be selectively enabled or disabled.

5.7.4.5.1 Interrupts Electrical Data and Timing

Table 5-13 Timing Requirements for Interrupts⁽¹⁾ (see Figure 5-19)

NO.			CV_DD = 1.05 V CV_DD = 1.3 V CV_DD = 1.4 V		UNIT
NO.			MIN	MAX	UNIT
1	t_w(INTH)	Pulse duration, interrupt high CPU active	2P		ns
2	t_w(INTL)	Pulse duration, interrupt low CPU active	2P		ns

(1) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns. For example, when the CPU core is clocked at 175 MHz, use P = 5.71 ns.

Figure 5-19 External Interrupt Timings

5.7.4.5.2 Wake-Up From IDLE Electrical Data and Timing

Table 5-14 Timing Requirements for Wake-Up From IDLE (see Figure 5-20)

NO.			CV_DD = 1.05 V CV_DD = 1.3 V CV_DD = 1.4 V		UNIT
NO.			MIN	MAX	UNIT
1	t_w(WKPL)	Pulse duration, WAKEUP or INTx low, SYSCLKDIS = 1	30.5		μs

Table 5-15 Switching Characteristics Over Recommended Operating Conditions For Wake-Up From IDLE⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾ (see Figure 5-20)

NO.	PARAMETER			CV_DD = 1.05 V CV_DD = 1.3 V CV_DD = 1.4 V			UNIT
NO.	PARAMETER			MIN	TYP	MAX	UNIT
2	t_d(WKEVTH-C_KLGEN)	Delay time, WAKEUP pulse complete to CPU active	IDLE3 Mode⁽⁵⁾ with SYSCLKDIS = 1, WAKEUP or INTx event, CLK_SEL = 1	D			ns
			IDLE3 Mode⁽⁵⁾ with SYSCLKDIS = 1, WAKEUP or INTx event, CLK_SEL = 0	C			ns
			IDLE2 Mode⁽⁵⁾; INTx event	3P			ns

(1) D = 1/ External Clock Frequency (CLKIN).

(2) C = 1/RTCCLK= 30.5 µs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.

(3) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.

(4) Assumes the internal LDOs are used with a 0.1uF bandgap capacitor.

(5) For a description of IDLE2 and IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number SPRUH16].

A. INT[1:0] can only be used as a wake-up event for IDLE3 and IDLE2 modes.
For a description of IDLE2 and IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number SPRUH16].

B. RTC interrupt (internal signal) can be used as wake-up event for IDLE3 and IDLE2 modes.

C. Any unmasked interrupt can be used to exit the IDLE2 mode.

D. CLKOUT reflects either the CPU clock, SAR, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.

Figure 5-20 Wake-Up From IDLE Timings ABC

5.7.4.5.3 XF Electrical Data and Timing

Table 5-16 Switching Characteristics Over Recommended Operating Conditions For XF⁽³⁾⁽²⁾
(see Figure 5-21)

NO.	PARAMETER			CV_DD = 1.05 V CV_DD = 1.3 V CV_DD = 1.4 V		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
1	t_d(XF)	Delay time, CLKOUT high to XF high		0	10.2	ns

A. CLKOUT reflects either the CPU clock, SAR, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.

Figure 5-21 XF Timings

5.7.5 Direct Memory Access (DMA) Controller

The DMA controller is used to move data among internal memory, external memory, and peripherals without intervention from the CPU and in the background of CPU operation.

The DSP includes a total of four DMA controllers. Aside from the DSP resources they can access, all four DMA controllers are identical.

The DMA controller has the following features:

Operation that is independent of the CPU.
Four channels, which allow the DMA controller to keep track of the context of four independent block transfers.
Event synchronization. DMA transfers in each channel can be made dependent on the occurrence of selected events.
An interrupt for each channel. Each channel can send an interrupt to the CPU on completion of the programmed transfer.
Ping-Pong mode allows the DMA controller to keep track of double buffering context without CPU intervention.
A dedicated clock idle domain. The four device DMA controllers can be put into a low-power state by independently turning off their input clocks.

5.7.5.1 DMA Channel Synchronization Events

The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP supports 20 separate synchronization events and each channel can be tied to separate sync events independent of the other channels. Synchronization events are selected by programming the CHnEVT field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2).

5.7.6 External Memory Interface (EMIF)

The device supports several memories and external device interfaces, including: NOR Flash, NAND Flash, SRAM, Non-Mobile SDRAM, and Mobile SDRAM (mSDRAM).

Note: The device can support non-mobile SDRAM under certain circumstances. The device also always uses mobile SDRAM initialization, but it is able to support SDRAM memories that ignore the BA0 and BA1 pins for the 'load mode register' command. During the mobile SDRAM initialization, the device issues the 'load mode register' initialization command to two different addresses that differ in only the BA0 and BA1 address bits. These registers are the Extended Mode register and the Mode register. The Extended mode register exists only in mSDRAM and not in non-mSDRAM. If a non-mobile SDRAM memory ignores bits BA0 and BA1, the second loaded register value overwrites the first, leaving the desired value in the Mode register and the non-mobile SDRAM will work with the device.

The EMIF provides an 8-bit or 16-bit data bus, an address bus width up to 21 bits, and 6 chip selects, along with memory control signals.

The EM_A[20:15] address signals are multiplexed with the GPIO peripheral and controlled by the External Bus Selection Register (EBSR). For more detail on the pin muxing, see Section 5.7.3.5.1, External Bus Selection Register (EBSR).

5.7.6.1 EMIF Asynchronous Memory Support

The EMIF supports asynchronous:

SRAM memories
NAND Flash memories
NOR Flash memories

The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address lines and four external wait and interrupt inputs. Up to four asynchronous chip selects are supported by EMIF (EM_CS[5:2]).

Each chip select has the following individually programmable attributes:

Data bus width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes

Each chip select shares the following programmable attribute: Extended Wait Option with Programmable Timeout.

5.7.6.2 EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported

The EMIF supports 16-bit non-mobile and mobile single data rate (SDR) SDRAM in addition to the asynchronous memories listed in Section 5.7.6.1, EMIF Asynchronous Memory Support. The supported SDRAM and mobile SDRAM configurations are:

One, two, and four bank SDRAM and mSDRAM devices
Supports devices with eight, nine, ten, and eleven column addresses
CAS latency of two or three clock cycles
16-bit data-bus width
3.3-, 2.75-, and 1.8 -V LVCMOS interface that is separate from the rest of the chip I/Os.
One (EM_CS0) or two (EM_CS[1:0]) chip selects

Additionally, the SDRAM and mSDRAM interface of EMIF supports placing the SDRAM and mSDRAM in "Self-Refresh" and "Powerdown Modes". Self-Refresh mode allows the SDRAM and mSDRAM to be put into a low-power state while still retaining memory contents; since the SDRAM and mSDRAM will continue to refresh itself even without clocks from the DSP. Powerdown mode achieves even lower power, except the DSP must periodically wake the SDRAM and mSDRAM up and issue refreshes if data retention is required. To achieve the lowest power consumption, the SDRAM and mSDRAM interface has configurable slew rate on the EMIF pins.

The device has limitations to the clock frequency on the EM_SDCLK pin based on the CV_DD and DV_DDEMIF:

The clock frequency on the EM_SDCLK pin can be configured either as SYSCLK (DSP operating frequency) or SYSCLK/2 via bit 0 of the ECDR Register (1C26h).
When CV_DD = 1.3 V or 1.4 V, and DV_DDEMIF = 3.3 V or 2.75 V, the max clock frequency on the EM_SDCLK pin is limited to 100 MHz (EM_SDCLK = 100 MHz). Therefore, if SYSCLK ≤ 100 MHz, the EM_SDCLK can be configured either as SYSCLK or SYSCLK/2. If SYSCLK > 100 MHz, the EM_SDCLK must be configured as SYSCLK/2 and ≤ 100 MHz.
When CV_DD =1.05 V, and DV_DDEMIF = 3.3 V or 2.75 V, the max clock frequency on the EM_SDCLK pin is limited to 75 MHz (EM_SDCLK = 75 MHz). Therefore, if SYSCLK ≤ 75 MHz, the EM_SDCLK can be configured as either SYSCLK or SYSCLK/2. If SYSCLK > 75 MHz, the EM_SDCLK must be configured as SYSCLK/2 and ≤ 75 MHz.
When DV_DDEMIF = 1.8 V, regardless of the CV_DD voltage, the clock frequency on the EM_SDCLK pin must be configured as SYSCLK/2 and ≤ 50 MHz.