SPRSP61C October   2021  – December 2023 TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for PZ Package
    8. 6.8  Thermal Resistance Characteristics for PN Package
    9. 6.9  Thermal Resistance Characteristics for PM Package
    10. 6.10 Thermal Resistance Characteristics for PT Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1 Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 6.12.2 Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.12.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3 Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks and PLLs
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
              1. 6.12.3.4.3.3.1 X1/X2 Precondition
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Oscillator Parameters
            2. 6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.12.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4 Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5 RAM and ROM Parameters
      6. 6.12.6 Emulation/JTAG
        1. 6.12.6.1 JTAG Electrical Data and Timing
          1. 6.12.6.1.1 JTAG Timing Requirements
          2. 6.12.6.1.2 JTAG Switching Characteristics
          3. 6.12.6.1.3 JTAG Timing Diagram
        2. 6.12.6.2 cJTAG Electrical Data and Timing
          1. 6.12.6.2.1 cJTAG Timing Requirements
          2. 6.12.6.2.2 cJTAG Switching Characteristics
          3. 6.12.6.2.3 cJTAG Timing Diagram
      7. 6.12.7 GPIO Electrical Data and Timing
        1. 6.12.7.1 GPIO – Output Timing
          1. 6.12.7.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.7.1.2 General-Purpose Output Timing Diagram
        2. 6.12.7.2 GPIO – Input Timing
          1. 6.12.7.2.1 General-Purpose Input Timing Requirements
          2. 6.12.7.2.2 Sampling Mode
        3. 6.12.7.3 Sampling Window Width for Input Signals
      8. 6.12.8 Interrupts
        1. 6.12.8.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.8.1.1 External Interrupt Timing Requirements
          2. 6.12.8.1.2 External Interrupt Switching Characteristics
          3. 6.12.8.1.3 External Interrupt Timing
      9. 6.12.9 Low-Power Modes
        1. 6.12.9.1 Clock-Gating Low-Power Modes
        2. 6.12.9.2 Low-Power Mode Wake-up Timing
          1. 6.12.9.2.1 IDLE Mode Timing Requirements
          2. 6.12.9.2.2 IDLE Mode Switching Characteristics
          3. 6.12.9.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.9.2.4 STANDBY Mode Timing Requirements
          5. 6.12.9.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.9.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.9.2.7 HALT Mode Timing Requirements
          8. 6.12.9.2.8 HALT Mode Switching Characteristics
          9. 6.12.9.2.9 HALT Entry and Exit Timing Diagram
    13. 6.13 Analog Peripherals
      1. 6.13.1 Analog Pins and Internal Connections
      2. 6.13.2 Analog Signal Descriptions
      3. 6.13.3 Analog-to-Digital Converter (ADC)
        1. 6.13.3.1 ADC Configurability
          1. 6.13.3.1.1 Signal Mode
        2. 6.13.3.2 ADC Electrical Data and Timing
          1. 6.13.3.2.1 ADC Operating Conditions
          2. 6.13.3.2.2 ADC Characteristics
          3. 6.13.3.2.3 ADC Input Model
          4. 6.13.3.2.4 ADC Timing Diagrams
      4. 6.13.4 Temperature Sensor
        1. 6.13.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.4.1.1 Temperature Sensor Characteristics
      5. 6.13.5 Comparator Subsystem (CMPSS)
        1. 6.13.5.1 CMPSS Connectivity Diagram
        2. 6.13.5.2 Block Diagram
        3. 6.13.5.3 CMPSS Electrical Data and Timing
          1. 6.13.5.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.5.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.5.3.3 CMPSS Illustrative Graphs
          5. 6.13.5.3.4 CMPSS DAC Dynamic Error
      6. 6.13.6 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.6.1 Buffered DAC Electrical Data and Timing
          1. 6.13.6.1.1 Buffered DAC Operating Conditions
          2. 6.13.6.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 Control Peripherals
      1. 6.14.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.1.1 ePWM Electrical Data and Timing
          1. 6.14.1.1.1 ePWM Timing Requirements
          2. 6.14.1.1.2 ePWM Switching Characteristics
          3. 6.14.1.1.3 Trip-Zone Input Timing
            1. 6.14.1.1.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.1.1.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.14.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.2.1 HRPWM Electrical Data and Timing
          1. 6.14.2.1.1 High-Resolution PWM Characteristics
      3. 6.14.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.14.4 Enhanced Capture (eCAP)
        1. 6.14.4.1 eCAP and HRCAP Block Diagram
        2. 6.14.4.2 eCAP Synchronization
        3. 6.14.4.3 eCAP Electrical Data and Timing
          1. 6.14.4.3.1 eCAP Timing Requirements
          2. 6.14.4.3.2 eCAP Switching Characteristics
      5. 6.14.5 High-Resolution Capture (HRCAP)
        1. 6.14.5.1 eCAP and HRCAP Block Diagram
        2. 6.14.5.2 HRCAP Electrical Data and Timing
          1. 6.14.5.2.1 HRCAP Switching Characteristics
          2. 6.14.5.2.2 HRCAP Figure and Graph
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO - ASYNC - Option
    15. 6.15 Communications Peripherals
      1. 6.15.1 Controller Area Network (CAN)
      2. 6.15.2 Modular Controller Area Network (MCAN)
      3. 6.15.3 Inter-Integrated Circuit (I2C)
        1. 6.15.3.1 I2C Electrical Data and Timing
          1. 6.15.3.1.1 I2C Timing Requirements
          2. 6.15.3.1.2 I2C Switching Characteristics
          3. 6.15.3.1.3 I2C Timing Diagram
      4. 6.15.4 Power Management Bus (PMBus) Interface
        1. 6.15.4.1 PMBus Electrical Data and Timing
          1. 6.15.4.1.1 PMBus Electrical Characteristics
          2. 6.15.4.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.4.1.3 PMBus Standard Mode Switching Characteristics
      5. 6.15.5 Serial Communications Interface (SCI)
      6. 6.15.6 Serial Peripheral Interface (SPI)
        1. 6.15.6.1 SPI Master Mode Timings
          1. 6.15.6.1.1 SPI Master Mode Timing Requirements
          2. 6.15.6.1.2 SPI Master Mode Switching Characteristics - Clock Phase  0
          3. 6.15.6.1.3 SPI Master Mode Switching Characteristics - Clock Phase  1
          4. 6.15.6.1.4 SPI Master Mode Timing Diagrams
        2. 6.15.6.2 SPI Slave Mode Timings
          1. 6.15.6.2.1 SPI Slave Mode Timing Requirements
          2. 6.15.6.2.2 SPI Slave Mode Switching Characteristics
          3. 6.15.6.2.3 SPI Slave Mode Timing Diagrams
      7. 6.15.7 Local Interconnect Network (LIN)
      8. 6.15.8 Fast Serial Interface (FSI)
        1. 6.15.8.1 FSI Transmitter
          1. 6.15.8.1.1 FSITX Electrical Data and Timing
            1. 6.15.8.1.1.1 FSITX Switching Characteristics
            2. 6.15.8.1.1.2 FSITX Timings
        2. 6.15.8.2 FSI Receiver
          1. 6.15.8.2.1 FSIRX Electrical Data and Timing
            1. 6.15.8.2.1.1 FSIRX Timing Requirements
            2. 6.15.8.2.1.2 FSIRX Switching Characteristics
            3. 6.15.8.2.1.3 FSIRX Timings
        3. 6.15.8.3 FSI SPI Compatibility Mode
          1. 6.15.8.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.8.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.8.3.1.2 FSITX SPI Signaling Mode Timings
      9. 6.15.9 Host Interface Controller (HIC)
        1. 6.15.9.1 HIC Electrical Data and Timing
          1. 6.15.9.1.1 HIC Timing Requirements
          2. 6.15.9.1.2 HIC Switching Characteristics
          3. 6.15.9.1.3 HIC Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Fast Integer Division Unit
      3. 7.6.3 Trigonometric Math Unit (TMU)
      4. 7.6.4 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Background CRC-32 (BGCRC)
    10. 7.10 Direct Memory Access (DMA)
    11. 7.11 Device Boot Modes
      1. 7.11.1 Device Boot Configurations
        1. 7.11.1.1 Configuring Boot Mode Pins
        2. 7.11.1.2 Configuring Boot Mode Table Options
      2. 7.11.2 GPIO Assignments
    12. 7.12 Security
      1. 7.12.1 Securing the Boundary of the Chip
        1. 7.12.1.1 JTAGLOCK
        2. 7.12.1.2 Zero-pin Boot
      2. 7.12.2 Dual-Zone Security
      3. 7.12.3 Disclaimer
    13. 7.13 Watchdog
    14. 7.14 C28x Timers
    15. 7.15 Dual-Clock Comparator (DCC)
      1. 7.15.1 Features
      2. 7.15.2 Mapping of DCCx Clock Source Inputs
    16. 7.16 Configurable Logic Block (CLB)
    17. 7.17 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Applications and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Automotive Pump
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Automotive Pump Resources
        2. 8.3.1.2 Automotive HVAC Compressor
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 HVAC Resources
        3. 8.3.1.3 On-Board Charger (OBC)
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 OBC Resources
        4. 8.3.1.4 Servo Drive Control Module
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Servo Drive Control Module Resources
        5. 8.3.1.5 Solar Micro Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 Solar Micro Inverter Resources
        6. 8.3.1.6 Merchant Telecom Rectifiers
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 Merchant Telecom Rectifiers Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.2 Digital Signals

Table 5-3 Digital Signals
SIGNAL NAME PIN TYPE DESCRIPTION GPIO 100 PZ 80 PN 64 PMQ 64 PM 48 PT
ADCSOCAO O ADC Start of Conversion A for External ADC 8, 33, 53 12, 53, 74 38, 58 32, 47 32, 47 25
ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32, 54 13, 64, 93 49, 76 40, 63 40, 63 32
AUXCLKIN I Auxiliary Clock Input 29 100 3 1 1 1
CANA_RX I CAN-A Receive 3, 5, 12, 18, 30, 33, 35, 49, 53, 59, 61 8, 12, 51, 53, 63, 68, 76, 89, 91, 92, 98 1, 36, 38, 48, 50, 60, 74 30, 32, 39, 41, 49, 61 30, 32, 39, 41, 49, 61 25, 31, 33, 39, 47
CANA_TX O CAN-A Transmit 2, 4, 13, 17, 19, 31, 32, 37, 48, 58 7, 50, 55, 61, 64, 67, 69, 75, 77, 99 2, 35, 40, 46, 49, 51, 59, 61 29, 34, 37, 40, 42, 48, 50 29, 34, 37, 40, 42, 48, 50 29, 32, 34, 38, 40
CLB_OUTPUTXBAR1 O CLB Output X-BAR Output 1 19, 22 69, 83 51, 67 42, 56 42, 56 34
CLB_OUTPUTXBAR2 O CLB Output X-BAR Output 2 7, 39, 47 6, 84 56, 68 57 46, 57 43
CLB_OUTPUTXBAR3 O CLB Output X-BAR Output 3 23, 42, 44 81, 85 57, 65, 69 54 54
CLB_OUTPUTXBAR4 O CLB Output X-BAR Output 4 10, 43, 45 93 54, 73, 76 63 63
CLB_OUTPUTXBAR5 O CLB Output X-BAR Output 5 5, 8, 52 11, 74, 89 58, 74 47, 61 47, 61 47
CLB_OUTPUTXBAR6 O CLB Output X-BAR Output 6 4, 15, 53 12, 75, 95 59, 78 48 48 38
CLB_OUTPUTXBAR7 O CLB Output X-BAR Output 7 1, 14, 56 65, 78, 96 62, 79 51 51 41
CLB_OUTPUTXBAR8 O CLB Output X-BAR Output 8 0, 6, 57 66, 79, 97 63, 80 52, 64 52, 64 42, 48
EPWM1_A O ePWM-1 Output A 0, 30 79, 98 1, 63 52 52 42
EPWM1_B O ePWM-1 Output B 1, 31 78, 99 2, 62 51 51 41
EPWM2_A O ePWM-2 Output A 2, 41 77, 82 61, 66 50, 55 50, 55 40
EPWM2_B O ePWM-2 Output B 3, 40 76, 80 60, 64 49, 53 49, 53 39
EPWM3_A O ePWM-3 Output A 4, 14 75, 96 59, 79 48 48 38
EPWM3_B O ePWM-3 Output B 5, 15 89, 95 74, 78 61 61 47
EPWM4_A O ePWM-4 Output A 6, 22 83, 97 67, 80 56, 64 56, 64 48
EPWM4_B O ePWM-4 Output B 7, 23 81, 84 65, 68 54, 57 54, 57 43
EPWM5_A O ePWM-5 Output A 8, 16 54, 74 39, 58 33, 47 33, 47 26
EPWM5_B O ePWM-5 Output B 9, 17, 35 55, 63, 90 40, 48, 75 34, 39, 62 34, 39, 62 31
EPWM6_A O ePWM-6 Output A 10, 18 68, 93 50, 76 41, 63 41, 63 33
EPWM6_B O ePWM-6 Output B 11, 19 52, 69 37, 51 31, 42 31, 42 34
EPWM7_A O ePWM-7 Output A 12, 28 1, 51 4, 36 2, 30 2, 30 2
EPWM7_B O ePWM-7 Output B 13, 29 50, 100 3, 35 1, 29 1, 29 1
EPWM8_A O ePWM-8 Output A 14, 24 56, 96 41, 79 35 35 27
EPWM8_B O ePWM-8 Output B 15, 32 64, 95 49, 78 40 40 32
EQEP1_A I eQEP-1 Input A 6, 10, 20, 25, 28, 35, 40, 44, 50, 56 1, 9, 48, 57, 63, 65, 80, 85, 93, 97 4, 33, 42, 48, 64, 69, 76, 80 2, 39, 53, 63, 64 2, 39, 53, 63, 64 2, 31, 48
EQEP1_B I eQEP-1 Input B 7, 11, 21, 29, 37, 41, 51, 57 10, 49, 52, 61, 66, 82, 84, 100 3, 34, 37, 46, 66, 68 1, 31, 37, 55, 57 1, 31, 37, 55, 57 1, 29, 43
EQEP1_INDEX I/O eQEP-1 Index 0, 9, 13, 17, 23, 31, 39, 43, 53, 59 12, 50, 55, 79, 81, 90, 92, 99 2, 35, 40, 54, 56, 63, 65, 75 29, 34, 52, 54, 62 29, 34, 46, 52, 54, 62 42
EQEP1_STROBE I/O eQEP-1 Strobe 8, 12, 16, 22, 30, 42, 52, 58 11, 51, 54, 67, 74, 83, 98 1, 36, 39, 57, 58, 67 30, 33, 47, 56 30, 33, 47, 56 26
EQEP2_A I eQEP-2 Input A 11, 14, 18, 24, 54 13, 52, 56, 68, 96 37, 41, 50, 79 31, 35, 41 31, 35, 41 27, 33
EQEP2_B I eQEP-2 Input B 15, 16, 19, 25, 33, 55 43, 53, 54, 57, 69, 95 38, 39, 42, 51, 78 32, 33, 42 32, 33, 42 25, 26, 34
EQEP2_INDEX I/O eQEP-2 Index 26, 29, 39, 57 58, 66, 100 3, 43, 56 1 1, 46 1
EQEP2_STROBE I/O eQEP-2 Strobe 4, 27, 28, 56 1, 59, 65, 75 4, 44, 59 2, 48 2, 48 2, 38
ERRORSTS O Error Status Output. This signal requires an external pulldown. 24, 28, 29, 55 1, 43, 56, 100 3, 4, 41 1, 2, 35 1, 2, 35 1, 2, 27
FSIRXA_CLK I FSIRX-A Input Clock 0, 4, 13, 30, 33, 39, 54, 57 13, 50, 53, 66, 75, 79, 98 1, 35, 38, 56, 59, 63 29, 32, 48, 52 29, 32, 46, 48, 52 25, 38, 42
FSIRXA_D0 I FSIRX-A Primary Data Input 3, 12, 32, 40, 44, 52, 58 11, 51, 64, 67, 76, 80, 85 36, 49, 60, 64, 69 30, 40, 49, 53 30, 40, 49, 53 32, 39
FSIRXA_D1 I FSIRX-A Optional Additional Data Input 2, 11, 31, 41, 53, 56 12, 52, 65, 77, 82, 99 2, 37, 61, 66 31, 50, 55 31, 50, 55 40
FSITXA_CLK O FSITX-A Output Clock 7, 10, 27, 44, 51 10, 59, 84, 85, 93 44, 68, 69, 76 57, 63 57, 63 43
FSITXA_D0 O FSITX-A Primary Data Output 6, 9, 26, 45, 49 8, 58, 90, 97 43, 73, 75, 80 62, 64 62, 64 48
FSITXA_D1 O FSITX-A Optional Additional Data Output 5, 6, 8, 25, 46, 50 9, 57, 74, 89, 97 6, 42, 58, 74, 80 47, 61, 64 47, 61, 64 47, 48
FSITXA_TDM_CLK I FSITX-A Time Division Multiplexed Clock Input 8, 18, 47 6, 68, 74 50, 58 41, 47 41, 47 33
FSITXA_TDM_D0 I FSITX-A Time Division Multiplexed Data Input 10, 19 69, 93 51, 76 42, 63 42, 63 34
FSITXA_TDM_D1 I FSITX-A Time Division Multiplexed Additional Data Input 1, 54, 59 13, 78, 92 62 51 51 41
GPIO0 I/O General-Purpose Input Output 0 0 79 63 52 52 42
GPIO1 I/O General-Purpose Input Output 1 1 78 62 51 51 41
GPIO2 I/O General-Purpose Input Output 2 2 77 61 50 50 40
GPIO3 I/O General-Purpose Input Output 3 3 76 60 49 49 39
GPIO4 I/O General-Purpose Input Output 4 4 75 59 48 48 38
GPIO5 I/O General-Purpose Input Output 5 5 89 74 61 61 47
GPIO6 I/O General-Purpose Input Output 6 6 97 80 64 64 48
GPIO7 I/O General-Purpose Input Output 7 7 84 68 57 57 43
GPIO8 I/O General-Purpose Input Output 8 8 74 58 47 47
GPIO9 I/O General-Purpose Input Output 9 9 90 75 62 62
GPIO10 I/O General-Purpose Input Output 10 10 93 76 63 63
GPIO11 I/O General-Purpose Input Output 11 11 52 37 31 31
GPIO12 I/O General-Purpose Input Output 12 12 51 36 30 30
GPIO13 I/O General-Purpose Input Output 13 13 50 35 29 29
GPIO14 I/O General-Purpose Input Output 14 14 96 79
GPIO15 I/O General-Purpose Input Output 15 15 95 78
GPIO16 I/O General-Purpose Input Output 16 16 54 39 33 33 26
GPIO17 I/O General-Purpose Input Output 17 17 55 40 34 34
GPIO18 I/O General-Purpose Input Output 18 18 68 50 41 41 33
GPIO19 I/O General-Purpose Input Output 19 19 69 51 42 42 34
GPIO20 I/O General-Purpose Input Output 20 20 48 33
GPIO21 I/O General-Purpose Input Output 21 21 49 34
GPIO22 I/O General-Purpose Input Output 22 22 83 67 56 56
GPIO23 I/O General-Purpose Input Output 23 23 81 65 54 54
GPIO24 I/O General-Purpose Input Output 24 24 56 41 35 35 27
GPIO25 I/O General-Purpose Input Output 25 25 57 42
GPIO26 I/O General-Purpose Input Output 26 26 58 43
GPIO27 I/O General-Purpose Input Output 27 27 59 44
GPIO28 I/O General-Purpose Input Output 28 28 1 4 2 2 2
GPIO29 I/O General-Purpose Input Output 29 29 100 3 1 1 1
GPIO30 I/O General-Purpose Input Output 30 30 98 1
GPIO31 I/O General-Purpose Input Output 31 31 99 2
GPIO32 I/O General-Purpose Input Output 32 32 64 49 40 40 32
GPIO33 I/O General-Purpose Input Output 33 33 53 38 32 32 25
GPIO34 I/O General-Purpose Input Output 34 34 94 77
GPIO35 I/O General-Purpose Input Output 35 35 63 48 39 39 31
GPIO37 I/O General-Purpose Input Output 37 37 61 46 37 37 29
GPIO39 I/O General-Purpose Input Output 39 39 56 46
GPIO40 I/O General-Purpose Input Output 40 40 80 64 53 53
GPIO41 I/O General-Purpose Input Output 41 41 82 66 55 55
GPIO42 I/O General-Purpose Input Output 42 42 57
GPIO43 I/O General-Purpose Input Output 43 43 54
GPIO44 I/O General-Purpose Input Output 44 44 85 69
GPIO45 I/O General-Purpose Input Output 45 45 73
GPIO46 I/O General-Purpose Input Output 46 46 6
GPIO47 I/O General-Purpose Input Output 47 47 6
GPIO48 I/O General-Purpose Input Output 48 48 7
GPIO49 I/O General-Purpose Input Output 49 49 8
GPIO50 I/O General-Purpose Input Output 50 50 9
GPIO51 I/O General-Purpose Input Output 51 51 10
GPIO52 I/O General-Purpose Input Output 52 52 11
GPIO53 I/O General-Purpose Input Output 53 53 12
GPIO54 I/O General-Purpose Input Output 54 54 13
GPIO55 I/O General-Purpose Input Output 55 55 43
GPIO56 I/O General-Purpose Input Output 56 56 65
GPIO57 I/O General-Purpose Input Output 57 57 66
GPIO58 I/O General-Purpose Input Output 58 58 67
GPIO59 I/O General-Purpose Input Output 59 59 92
GPIO60 I/O General-Purpose Input Output 60 60 44
GPIO61 I/O General-Purpose Input Output 61 61 91
HIC_A0 I HIC Address 0 8, 55, 60 14, 43, 44, 74 10, 58 6, 47 6, 47 4
HIC_A1 I HIC Address 1 2, 26 15, 58, 77 11, 43, 61 7, 50 7, 50 4, 40
HIC_A2 I HIC Address 2 1 16, 78 12, 62 8, 51 8, 51 5, 41
HIC_A3 I HIC Address 3 23 17, 81 13, 65 9, 54 9, 54 6
HIC_A4 I HIC Address 4 27, 41 59, 82 14, 44, 66 10, 55 10, 55 7
HIC_A5 I HIC Address 5 22 19, 83 15, 67 11, 56 11, 56
HIC_A6 I HIC Address 6 7, 42, 47 6, 20, 84 16, 57, 68 12, 57 12, 57 8, 43
HIC_A7 I HIC Address 7 5, 43, 48 7, 21, 89 17, 54, 74 13, 61 13, 61 9, 47
HIC_BASESEL0 I HIC Base address range select 0 9, 25 22, 57, 90 18, 42, 75 14, 62 14, 62 10
HIC_BASESEL1 I HIC Base address range select 1 0 23, 79 19, 63 15, 52 15, 52 11, 42
HIC_BASESEL2 I HIC Base address range select 2 4 40, 75 29, 59 25, 48 25, 48 21, 38
HIC_D0 I/O HIC Data 0 26, 33 53, 58 38, 43 32 32 25
HIC_D1 I/O HIC Data 1 16, 27 54, 59 39, 44 33 33 26
HIC_D2 I/O HIC Data 2 17, 42, 49 8, 55 40, 57 34 34
HIC_D3 I/O HIC Data 3 24, 43, 50 9, 56 41, 54 35 35 27
HIC_D4 I/O HIC Data 4 3, 5, 57 66, 76, 89 60, 74 49, 61 49, 61 39, 47
HIC_D5 I/O HIC Data 5 13, 40, 44 50, 80, 85 35, 64, 69 29, 53 29, 53
HIC_D6 I/O HIC Data 6 11, 45, 51, 56 10, 52, 65 37, 73 31 31
HIC_D7 I/O HIC Data 7 0, 39, 44 79, 85 56, 63, 69 52 46, 52 42
HIC_D8 I/O HIC Data 8 8, 30 74, 98 1, 58 47 47
HIC_D9 I/O HIC Data 9 2, 34 77, 94 61, 77 50 50 40
HIC_D10 I/O HIC Data 10 1, 31 78, 99 2, 62 51 51 41
HIC_D11 I/O HIC Data 11 13, 23 50, 81 35, 65 29, 54 29, 54
HIC_D12 I/O HIC Data 12 15, 41 82, 95 66, 78 55 55
HIC_D13 I/O HIC Data 13 12, 22 51, 83 36, 67 30, 56 30, 56
HIC_D14 I/O HIC Data 14 6, 7 84, 97 68, 80 57, 64 57, 64 43, 48
HIC_D15 I/O HIC Data 15 5, 14 89, 96 74, 79 61 61 47
HIC_INT O HIC Device interrupt to host 12, 18, 32 51, 64, 68 36, 49, 50 30, 40, 41 30, 40, 41 32, 33
HIC_NBE0 I HIC Byte enable 0 11, 19 38, 52, 69 28, 37, 51 24, 31, 42 24, 31, 42 20, 34
HIC_NBE1 I HIC Byte enable 1 6, 34, 40 37, 80, 94, 97 24, 64, 77, 80 20, 53, 64 20, 53, 64 16, 48
HIC_NCS I HIC Chip select input 29 28, 100 3, 22 1, 18 1, 18 1, 14
HIC_NOE O HIC Output enable for data bus 3, 28 1, 31, 76 4, 23, 60 2, 19, 49 2, 19, 49 2, 15, 39
HIC_NRDY O HIC Ready from device to host 9, 37, 58 61, 67, 90 46, 75 37, 62 37, 62 29
HIC_NWE I HIC Data Write enable from host 4, 10, 35, 46, 52 11, 36, 63, 75, 93 6, 27, 48, 59, 76 23, 39, 48, 63 23, 39, 48, 63 19, 31, 38
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 1, 8, 18, 27, 33, 37, 43, 57 53, 59, 61, 66, 68, 74, 78 38, 44, 46, 50, 54, 58, 62 32, 37, 41, 47, 51 32, 37, 41, 47, 51 25, 29, 33, 41
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 0, 10, 19, 26, 32, 35, 42, 56 58, 63, 64, 65, 69, 79, 93 43, 48, 49, 51, 57, 63, 76 39, 40, 42, 52, 63 39, 40, 42, 52, 63 31, 32, 34, 42
I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock 3, 9, 15, 29, 51 10, 76, 90, 95, 100 3, 60, 75, 78 1, 49, 62 1, 49, 62 1, 39
I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data 2, 14, 28, 34, 50 1, 9, 77, 94, 96 4, 61, 77, 79 2, 50 2, 50 2, 40
LINA_RX I LIN-A Receive 23, 29, 33, 35, 42, 47, 49, 59 6, 8, 53, 63, 81, 92, 100 3, 38, 48, 57, 65 1, 32, 39, 54 1, 32, 39, 54 1, 25, 31
LINA_TX O LIN-A Transmit 22, 28, 32, 37, 46, 58 1, 61, 64, 67, 83 4, 6, 46, 49, 67 2, 37, 40, 56 2, 37, 40, 56 2, 29, 32
LINB_RX I LIN-B Receive 9, 11, 13, 15, 19, 23, 41, 55 43, 50, 52, 69, 81, 82, 90, 95 35, 37, 51, 65, 66, 75, 78 29, 31, 42, 54, 55, 62 29, 31, 42, 54, 55, 62 34
LINB_TX O LIN-B Transmit 10, 12, 14, 18, 22, 24, 40, 44, 54 13, 51, 56, 68, 80, 83, 85, 93, 96 36, 41, 50, 64, 67, 69, 76, 79 30, 35, 41, 53, 56, 63 30, 35, 41, 53, 56, 63 27, 33
MCAN_RX I CAN/CAN FD Receive 0, 5, 12, 21, 30, 39, 47, 51, 57, 61 6, 10, 49, 51, 66, 79, 89, 91, 98 1, 34, 36, 56, 63, 74 30, 52, 61 30, 46, 52, 61 42, 47
MCAN_TX O CAN/CAN FD Transmit 1, 4, 13, 20, 31, 46, 50, 56, 60 9, 44, 48, 50, 65, 75, 78, 99 2, 6, 33, 35, 59, 62 29, 48, 51 29, 48, 51 38, 41
OUTPUTXBAR1 O Output X-BAR Output 1 2, 24, 34, 58 56, 67, 77, 94 41, 61, 77 35, 50 35, 50 27, 40
OUTPUTXBAR2 O Output X-BAR Output 2 3, 25, 37, 54, 59 13, 57, 61, 76, 92 42, 46, 60 37, 49 37, 49 29, 39
OUTPUTXBAR3 O Output X-BAR Output 3 4, 5, 14, 26, 48, 55, 60 7, 43, 44, 58, 75, 89, 96 43, 59, 74, 79 48, 61 48, 61 38, 47
OUTPUTXBAR4 O Output X-BAR Output 4 6, 15, 27, 33, 49, 61 8, 53, 59, 91, 95, 97 38, 44, 78, 80 32, 64 32, 64 25, 48
OUTPUTXBAR5 O Output X-BAR Output 5 7, 28, 42 1, 84 4, 57, 68 2, 57 2, 57 2, 43
OUTPUTXBAR6 O Output X-BAR Output 6 9, 29, 43 90, 100 3, 54, 75 1, 62 1, 62 1
OUTPUTXBAR7 O Output X-BAR Output 7 11, 16, 30, 44 52, 54, 85, 98 1, 37, 39, 69 31, 33 31, 33 26
OUTPUTXBAR8 O Output X-BAR Output 8 17, 31, 45 55, 99 2, 40, 73 34 34
PMBUSA_ALERT I/OD PMBus-A Open-Drain Bidirectional Alert Signal 13, 19, 27, 37, 43, 45 50, 59, 61, 69 35, 44, 46, 51, 54, 73 29, 37, 42 29, 37, 42 29, 34
PMBUSA_CTL I/O PMBus-A Control Signal - Slave Input/Master Output 12, 18, 26, 35, 42, 44 51, 58, 63, 68, 85 36, 43, 48, 50, 57, 69 30, 39, 41 30, 39, 41 31, 33
PMBUSA_SCL I/OD PMBus-A Open-Drain Bidirectional Clock 3, 15, 16, 24, 35, 41, 47 6, 54, 56, 63, 76, 82, 95 39, 41, 48, 60, 66, 78 33, 35, 39, 49, 55 33, 35, 39, 49, 55 26, 27, 31, 39
PMBUSA_SDA I/OD PMBus-A Open-Drain Bidirectional Data 2, 14, 17, 25, 32, 34, 40, 44, 46, 48 7, 55, 57, 64, 77, 80, 85, 94, 96 6, 40, 42, 49, 61, 64, 69, 77, 79 34, 40, 50, 53 34, 40, 50, 53 32, 40
SCIA_RX I SCI-A Receive Data 3, 9, 17, 25, 28, 35, 49 1, 8, 55, 57, 63, 76, 90 4, 40, 42, 48, 60, 75 2, 34, 39, 49, 62 2, 34, 39, 49, 62 2, 31, 39
SCIA_TX O SCI-A Transmit Data 2, 8, 16, 24, 29, 37, 48 7, 54, 56, 61, 74, 77, 100 3, 39, 41, 46, 58, 61 1, 33, 35, 37, 47, 50 1, 33, 35, 37, 47, 50 1, 26, 27, 29, 40
SCIB_RX I SCI-B Receive Data 11, 13, 15, 19, 23, 41, 57 50, 52, 66, 69, 81, 82, 95 35, 37, 51, 65, 66, 78 29, 31, 42, 54, 55 29, 31, 42, 54, 55 34
SCIB_TX O SCI-B Transmit Data 9, 10, 12, 14, 18, 22, 40, 56 51, 65, 68, 80, 83, 90, 93, 96 36, 50, 64, 67, 75, 76, 79 30, 41, 53, 56, 62, 63 30, 41, 53, 56, 62, 63 33
SD1_C1 I SDFM-1 Channel 1 Clock Input 17, 33, 49, 53 8, 12, 23, 53, 55 19, 38, 40 15, 32, 34 15, 32, 34 11, 25
SD1_C2 I SDFM-1 Channel 2 Clock Input 19, 33, 51, 54 10, 13, 31, 53, 69 23, 38, 51 19, 32, 42 19, 32, 42 15, 25, 34
SD1_C3 I SDFM-1 Channel 3 Clock Input 21, 53, 55 12, 38, 43, 49 28, 34 24 24 20
SD1_C4 I SDFM-1 Channel 4 Clock Input 23, 55, 56 40, 43, 65, 81 29, 65 25, 54 25, 54 21
SD1_D1 I SDFM-1 Channel 1 Data Input 16, 48 7, 19, 54 15, 39 11, 33 11, 33 26
SD1_D2 I SDFM-1 Channel 2 Data Input 18, 32, 50 9, 20, 64, 68 16, 49, 50 12, 40, 41 12, 40, 41 8, 32, 33
SD1_D3 I SDFM-1 Channel 3 Data Input 20, 52 11, 21, 48 17, 33 13 13 9
SD1_D4 I SDFM-1 Channel 4 Data Input 22, 54 13, 22, 83 18, 67 14, 56 14, 56 10
SD2_C1 I SDFM-2 Channel 1 Clock Input 25, 35, 57 14, 37, 57, 63, 66 10, 24, 42, 48 6, 20, 39 6, 20, 39 4, 16, 31
SD2_C2 I SDFM-2 Channel 2 Clock Input 27, 58, 59 36, 59, 67, 92 27, 44 23 23 19
SD2_C3 I SDFM-2 Channel 3 Clock Input 29, 45, 59, 61 28, 91, 92, 100 3, 22, 73 1, 18 1, 18 1, 14
SD2_C4 I SDFM-2 Channel 4 Clock Input 31, 46, 60 32, 44, 99 2, 6
SD2_D1 I SDFM-2 Channel 1 Data Input 24, 49, 56 8, 56, 65 14, 41 10, 35 10, 35 7, 27
SD2_D2 I SDFM-2 Channel 2 Data Input 26, 50, 58 9, 16, 58, 67 12, 43 8 8 5
SD2_D3 I SDFM-2 Channel 3 Data Input 28, 43, 51, 60 1, 10, 17, 44 4, 13, 54 2, 9 2, 9 2, 6
SD2_D4 I SDFM-2 Channel 4 Data Input 30, 47, 52 6, 11, 15, 98 1, 11 7 7 4
SPIA_CLK I/O SPI-A Clock 3, 9, 12, 18, 56 51, 65, 68, 76, 90 36, 50, 60, 75 30, 41, 49, 62 30, 41, 49, 62 33, 39
SPIA_SIMO I/O SPI-A Slave In, Master Out (SIMO) 2, 8, 11, 16, 54 13, 52, 54, 74, 77 37, 39, 58, 61 31, 33, 47, 50 31, 33, 47, 50 26, 40
SPIA_SOMI I/O SPI-A Slave Out, Master In (SOMI) 1, 10, 13, 17, 55 43, 50, 55, 78, 93 35, 40, 62, 76 29, 34, 51, 63 29, 34, 51, 63 41
SPIA_STE I/O SPI-A Slave Transmit Enable (STE) 0, 5, 11, 19, 57 52, 66, 69, 79, 89 37, 51, 63, 74 31, 42, 52, 61 31, 42, 52, 61 34, 42, 47
SPIB_CLK I/O SPI-B Clock 4, 14, 22, 26, 28, 32, 52, 58 1, 11, 58, 64, 67, 75, 83, 96 4, 43, 49, 59, 67, 79 2, 40, 48, 56 2, 40, 48, 56 2, 32, 38
SPIB_SIMO I/O SPI-B Slave In, Master Out (SIMO) 7, 20, 24, 30, 40, 50, 56, 60 9, 44, 48, 56, 65, 80, 84, 98 1, 33, 41, 64, 68 35, 53, 57 35, 53, 57 27, 43
SPIB_SOMI I/O SPI-B Slave Out, Master In (SOMI) 6, 16, 21, 25, 31, 41, 51, 57, 61 10, 49, 54, 57, 66, 82, 91, 97, 99 2, 34, 39, 42, 66, 80 33, 55, 64 33, 55, 64 26, 48
SPIB_STE I/O SPI-B Slave Transmit Enable (STE) 15, 23, 27, 29, 33, 53, 59 12, 53, 59, 81, 92, 95, 100 3, 38, 44, 65, 78 1, 32, 54 1, 32, 54 1, 25
SYNCOUT O External ePWM Synchronization Pulse 6, 39, 52 11, 97 56, 80 64 46, 64 48
TDI I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. 35 63 48 39 39 31
TDO O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. 37 61 46 37 37 29
X1 I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. See the XTAL section for usage details. 19 69 51 42 42 34
X2 I/O Crystal oscillator output. 18 68 50 41 41 33
XCLKOUT O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. 16, 18 54, 68 39, 50 33, 41 33, 41 26, 33