SPRSP19
December 2017
TMS320F28377D-EP
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Terminal Configuration and Functions
3.1
Pin Diagrams
3.2
Signal Descriptions
3.3
Pins With Internal Pullup and Pulldown
3.4
Pin Multiplexing
3.4.1
GPIO Muxed Pins
3.4.2
Input X-BAR
3.4.3
Output X-BAR and ePWM X-BAR
3.4.4
USB Pin Muxing
3.4.5
High-Speed SPI Pin Muxing
3.5
Connections for Unused Pins
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
Power Consumption Summary
4.4.1
Current Consumption Graphs
4.4.2
Reducing Current Consumption
4.5
Electrical Characteristics
4.6
Thermal Resistance Characteristics
4.6.1
GWT Package
4.6.2
PTP Package
4.7
System
4.7.1
Power Sequencing
4.7.2
Reset Timing
4.7.2.1
Reset Sources
4.7.2.2
Reset Electrical Data and Timing
4.7.3
Clock Specifications
4.7.3.1
Clock Sources
4.7.3.2
Clock Frequencies, Requirements, and Characteristics
4.7.3.2.1
Input Clock Frequency and Timing Requirements, PLL Lock Times
4.7.3.2.2
Internal Clock Frequencies
4.7.3.2.3
Output Clock Frequency and Switching Characteristics
4.7.3.3
Input Clocks and PLLs
4.7.3.4
Crystal Oscillator
4.7.3.5
Internal Oscillators
4.7.4
Flash Parameters
4.7.5
Emulation/JTAG
4.7.5.1
JTAG Electrical Data and Timing
4.7.6
GPIO Electrical Data and Timing
4.7.6.1
GPIO - Output Timing
4.7.6.2
GPIO - Input Timing
4.7.6.3
Sampling Window Width for Input Signals
4.7.7
Interrupts
4.7.7.1
External Interrupt (XINT) Electrical Data and Timing
4.7.8
Low-Power Modes
4.7.8.1
Clock-Gating Low-Power Modes
4.7.8.2
Power-Gating Low-Power Modes
4.7.8.3
Low-Power Mode Wakeup Timing
4.7.9
External Memory Interface (EMIF)
4.7.9.1
Asynchronous Memory Support
4.7.9.2
Synchronous DRAM Support
4.7.9.3
EMIF Electrical Data and Timing
4.7.9.3.1
Asynchronous RAM
4.7.9.3.2
Synchronous RAM
4.8
Analog Peripherals
4.8.1
Analog-to-Digital Converter (ADC)
4.8.1.1
ADC Electrical Data and Timing
4.8.1.1.1
ADC Input Models
4.8.1.1.2
ADC Timing Diagrams
4.8.1.2
Temperature Sensor Electrical Data and Timing
4.8.2
Comparator Subsystem (CMPSS)
4.8.2.1
CMPSS Electrical Data and Timing
4.8.3
Buffered Digital-to-Analog Converter (DAC)
4.8.3.1
Buffered DAC Electrical Data and Timing
4.9
Control Peripherals
4.9.1
Enhanced Capture (eCAP)
4.9.1.1
eCAP Electrical Data and Timing
4.9.2
Enhanced Pulse Width Modulator (ePWM)
4.9.2.1
Control Peripherals Synchronization
4.9.2.2
ePWM Electrical Data and Timing
4.9.2.2.1
Trip-Zone Input Timing
4.9.2.3
External ADC Start-of-Conversion Electrical Data and Timing
4.9.3
Enhanced Quadrature Encoder Pulse (eQEP)
4.9.3.1
eQEP Electrical Data and Timing
4.9.4
High-Resolution Pulse Width Modulator (HRPWM)
4.9.4.1
HRPWM Electrical Data and Timing
4.9.5
Sigma-Delta Filter Module (SDFM)
4.9.5.1
SDFM Electrical Data and Timing
4.10
Communications Peripherals
4.10.1
Controller Area Network (CAN)
4.10.2
Inter-Integrated Circuit (I2C)
4.10.2.1
I2C Electrical Data and Timing
4.10.3
Multichannel Buffered Serial Port (McBSP)
4.10.3.1
McBSP Electrical Data and Timing
4.10.3.1.1
McBSP Transmit and Receive Timing
4.10.3.1.2
McBSP as SPI Master or Slave Timing
4.10.4
Serial Communications Interface (SCI)
4.10.5
Serial Peripheral Interface (SPI)
4.10.5.1
SPI Electrical Data and Timing
4.10.5.1.1
Non-High-Speed Master Mode Timings
4.10.5.1.2
Non-High-Speed Slave Mode Timings
4.10.5.1.3
High-Speed Master Mode Timings
4.10.5.1.4
High-Speed Slave Mode Timings
4.10.6
Universal Serial Bus (USB) Controller
4.10.6.1
USB Electrical Data and Timing
4.10.7
Universal Parallel Port (uPP) Interface
4.10.7.1
uPP Electrical Data and Timing
5
Detailed Description
5.1
Overview
5.2
Functional Block Diagram
5.3
Memory
5.3.1
C28x Memory Map
5.3.2
Flash Memory Map
5.3.3
EMIF Chip Select Memory Map
5.3.4
Peripheral Registers Memory Map
5.3.5
Memory Types
5.3.5.1
Dedicated RAM (Mx and Dx RAM)
5.3.5.2
Local Shared RAM (LSx RAM)
5.3.5.3
Global Shared RAM (GSx RAM)
5.3.5.4
CPU Message RAM (CPU MSGRAM)
5.3.5.5
CLA Message RAM (CLA MSGRAM)
5.4
Identification
5.5
Bus Architecture - Peripheral Connectivity
5.6
C28x Processor
5.6.1
Floating-Point Unit
5.6.2
Trigonometric Math Unit
5.6.3
Viterbi, Complex Math, and CRC Unit II (VCU-II)
5.7
Control Law Accelerator
5.8
Direct Memory Access
5.9
Interprocessor Communication Module
5.10
Boot ROM and Peripheral Booting
5.10.1
EMU Boot or Emulation Boot
5.10.2
WAIT Boot Mode
5.10.3
Get Mode
5.10.4
Peripheral Pins Used by Bootloaders
5.11
Dual Code Security Module
5.12
Timers
5.13
Nonmaskable Interrupt With Watchdog Timer (NMIWD)
5.14
Watchdog
5.15
Configurable Logic Block (CLB)
6
Applications, Implementation, and Layout
6.1
TI Design or Reference Design
7
Device and Documentation Support
7.1
Device and Development Support Tool Nomenclature
7.2
Tools and Software
7.3
Device Nomenclature
7.4
Documentation Support
7.5
Community Resources
7.6
Trademarks
7.7
Electrostatic Discharge Caution
7.8
Export Control Notice
7.9
Glossary
8
Mechanical, Packaging, and Orderable Information
8.1
Via Channel
8.2
Packaging Information
Package Options
Mechanical Data (Package|Pins)
GWT|337
MPBGAY4
PTP|176
MPQF068B
Thermal pad, mechanical data (Package|Pins)
PTP|176
PPTD302A
Orderable Information
sprsp19_oa
sprsp19_pm
2
Revision History
DATE
REVISION
NOTES
December 2017
*
Initial Release