SCDS406A December   2018  – February 2024 TMUX1109

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (VDD = 5V ±10 %)
    6. 5.6 Electrical Characteristics (VDD = 3.3V ±10 %)
    7. 5.7 Electrical Characteristics (VDD = 2.5V ±10 %), (VSS = –2.5V ±10 %)
    8. 5.8 Electrical Characteristics (VDD = 1.8V ±10 %)
    9. 5.9 Electrical Characteristics (VDD = 1.2V ±10 %)
    10.     Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
      1. 6.1.1  On-Resistance
      2. 6.1.2  Off-Leakage Current
      3. 6.1.3  On-Leakage Current
      4. 6.1.4  Transition Time
      5. 6.1.5  Break-Before-Make
      6. 6.1.6  tON(EN) and tOFF(EN)
      7. 6.1.7  Charge Injection
      8. 6.1.8  Off Isolation
      9. 6.1.9  Crosstalk
      10. 6.1.10 Bandwidth
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Bidirectional Operation
      2. 6.3.2 Rail to Rail Operation
      3. 6.3.3 1.8V Logic Compatible Inputs
      4. 6.3.4 Fail-Safe Logic
      5. 6.3.5 Ultra-Low Leakage Current
      6. 6.3.6 Ultra-Low Charge Injection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Truth Tables
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • RSV|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 7-3 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.

GUID-C6469B5D-8CD2-48C0-A915-1C45CD4E15F3-low.gif Figure 7-3 Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies.

Figure 7-4 shows an example of a PCB layout with the TMUX1109. Some key considerations are:

  • Decouple the VDD pin with a 0.1µF capacitor, and place the capacitor as close to the pin as possible. Ensure that the capacitor voltage rating is sufficient for the VDD supply.
  • Keep the input lines as short as possible.
  • Use a solid ground plane to reduce electromagnetic interference (EMI) noise pickup.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.