SLASEW5A December   2020  – October 2024 TMUXHS4412

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 High-Speed Performance Parameters
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable and Power Savings
      2. 6.3.2 Data Line Biasing
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe Lane Muxing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Pin-to-Pin Passive Versus Redriver Option
        4. 7.2.1.4 Application Curves
    3. 7.3 Systems Examples
      1. 7.3.1 PCIe Muxing for Hybrid SSD
      2. 7.3.2 DisplayPort Main Link
      3. 7.3.3 USB 4.0 / TBT 3.0 Demuxing
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Related Documentation
      1. 8.1.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions


TMUXHS4412 RUA Package42-Pin WQFNTop View
Figure 4-1 RUA Package42-Pin WQFNTop View
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
D0P 3 I/O Common Port (D), channel 0, high-speed positive signal
D0N 4 I/O Common Port, channel 0, high-speed negative signal
D1P 7 I/O Common Port, channel 1, high-speed positive signal
D1N 8 I/O Common Port, channel 1, high-speed negative signal
D2P 10 I/O Common Port, channel 2, high-speed positive signal
D2N 11 I/O Common Port, channel 2, high-speed negative signal
D3P 14 I/O Common Port, channel 3, high-speed positive signal
D3N 15 I/O Common Port, channel 3, high-speed negative signal
DA0P 38 I/O Port A (DA), channel 0, high-speed positive signal
DA0N 37 I/O Port A, channel 0, high-speed negative signal
DA1P 34 I/O Port A, channel 1, high-speed positive signal
DA1N 33 I/O Port A, channel 1, high-speed negative signal
DA2P 29 I/O Port A, channel 2, high-speed positive signal
DA2N 28 I/O Port A, channel 2, high-speed negative signal
DA3P 25 I/O Port A, channel 3, high-speed positive signal
DA3N 24 I/O Port A, channel 3, high-speed negative signal
DB0P 36 I/O Port B (DB), channel 0, high-speed positive signal
DB0N 35 I/O Port B, channel 0, high-speed negative signal
DB1P 32 I/O Port B, channel 1, high-speed positive signal
DB1N 31 I/O Port B, channel 1, high-speed negative signal
DB2P 27 I/O Port B, channel 2, high-speed positive signal
DB2N 26 I/O Port B, channel 2, high-speed negative signal
DB3P 23 I/O Port B, channel 3, high-speed positive signal
DB3N 22 I/O Port B, channel 3, high-speed negative signal
GND 6, 9, 16, 21,30, 39 G Ground
PD 18 I Active-low chip enable.

H: Shutdown
NC 1, 2, 12, 19, 20, 40, 41 NA Leave unconnected
RSVD 42 NA Reserved - TI test mode. Pulldown to GND using a resistor such as 4.7kΩ
SEL 17 I

Port select pin.

L: Common Port (D) to Port A (DA)

H: Common Port (D) to Port B (DB)
VCC 5, 13 P 3.3 or 1.8V power