SLASEW5A December   2020  – October 2024 TMUXHS4412

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 High-Speed Performance Parameters
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable and Power Savings
      2. 6.3.2 Data Line Biasing
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe Lane Muxing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Pin-to-Pin Passive Versus Redriver Option
        4. 7.2.1.4 Application Curves
    3. 7.3 Systems Examples
      1. 7.3.1 PCIe Muxing for Hybrid SSD
      2. 7.3.2 DisplayPort Main Link
      3. 7.3.3 USB 4.0 / TBT 3.0 Demuxing
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Related Documentation
      1. 8.1.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Typical Characteristics

The following figures show differential insertion loss on the top plot and return loss on the bottom plot of a typical TMUXHS4412 channel. Note measurements are performed in TI evaluation board with board and equipment parasitics calibrated out.


TMUXHS4412 S-Parameter Plots for a TMUXHS4412 Channel: Differential Insertion Loss
Figure 5-1 S-Parameter Plots for a TMUXHS4412 Channel: Differential Insertion Loss

TMUXHS4412 S-Parameter Plots for a TMUXHS4412 Channel: Return Loss vs Frequency
Figure 5-2 S-Parameter Plots for a TMUXHS4412 Channel: Return Loss vs Frequency

The following figures show side-by-side comparisons of 10Gbps signals through calibration traces and a typical TMUXHS4412 channels.

TMUXHS4412 Jitter Decomposition of 10Gbps PRBS-7 Signals in TI Evaluation Board Through Calibration TracesFigure 5-3 Jitter Decomposition of 10Gbps PRBS-7 Signals in TI Evaluation Board Through Calibration Traces
TMUXHS4412 Jitter Decomposition of 10Gbps PRBS-7 Signals in TI Evaluation Board Through a Typical TMUXHS4412 ChannelFigure 5-4 Jitter Decomposition of 10Gbps PRBS-7 Signals in TI Evaluation Board Through a Typical TMUXHS4412 Channel

The following figures show side-by-side comparisons of 20Gbps signals through calibration traces and a typical TMUXHS4412 channels.

TMUXHS4412 Jitter Decomposition of 20Gbps PRBS-7 Signals in TI Evaluation Board Through Calibration Traces Figure 5-5 Jitter Decomposition of 20Gbps PRBS-7 Signals in TI Evaluation Board Through Calibration Traces
TMUXHS4412 Jitter Decomposition of 20Gbps PRBS-7 Signals in TI Evaluation Board Through a Typical TMUXHS4412 Channels Figure 5-6 Jitter Decomposition of 20Gbps PRBS-7 Signals in TI Evaluation Board Through a Typical TMUXHS4412 Channels