SLASEW5A December   2020  – October 2024 TMUXHS4412

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 High-Speed Performance Parameters
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable and Power Savings
      2. 6.3.2 Data Line Biasing
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe Lane Muxing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Pin-to-Pin Passive Versus Redriver Option
        4. 7.2.1.4 Application Curves
    3. 7.3 Systems Examples
      1. 7.3.1 PCIe Muxing for Hybrid SSD
      2. 7.3.2 DisplayPort Main Link
      3. 7.3.3 USB 4.0 / TBT 3.0 Demuxing
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Related Documentation
      1. 8.1.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.1.1 Design Requirements

Table 7-1 provides various parameters and the expected values to implement the PCIe lane switching topology. Note the recommendation is for illustration purpose only.
Table 7-1 Design Parameters
DESIGN PARAMETERVALUE

(VCC = 3.3V)

VALUE

(VCC = 1.8V)

Dx[P/N], DAx[P/N], DBx[P/N] CM input voltage0V to 1.8V0V to 0.9V

Must be biased from Dx[P/N] side)

SEL/PD pin max voltage for low<0.25 × VCC
SEL/PD pin min voltage for high>0.75 × VCC
AC coupling capacitor for PCIe TX pins75nF to 265nF
Decoupling capacitor for VCC0.1µF