SLOS417D October 2003 – November 2015 TPA2010D1
In making the pad size for the DSBGA balls, TI recommends that the layout use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 42 and Table 3 show the appropriate diameters for a DSBGA layout. The TPA2010D1 evaluation module (EVM) layout is shown in the next section as a layout example.
Follow these guidelines:
Place all the external components very close to the TPA2010D1. The input resistors need to be very close to the TPA2010D1 input pins so noise does not couple on the high impedance nodes between the input resistors and the input amplifier of the TPA2010D1. Placing the decoupling capacitor, CS, close to the TPA2010D1 is important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency.
Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB traces. Figure 40 shows the layout of the TPA2010D1 evaluation module (EVM).
For high current pins (VDD, GND VO+, and VO–) of the TPA2010D1, use 100-µm trace widths at the solder balls and at least 500-µm PCB traces to ensure proper performance and output power for the device.
For input pins (IN–, IN+, and SHUTDOWN) of the TPA2010D1, use 75-µm to 100-µm trace widths at the solder balls. IN– and IN+ pins need to run side-by-side to maximize common-mode noise cancellation. Placing input resistors, RIN, as close to the TPA2010D1 as possible is recommended.