SLOS417D October   2003  – November 2015 TPA2010D1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Device Comparison Table
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Operating Characteristics
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fully Differential Amplifier
      2. 8.3.2 Advantages of Fully Differential Amplifiers
      3. 8.3.3 Efficiency and Thermal Information
      4. 8.3.4 Eliminating the Output Filter With the TPA2010D1
        1. 8.3.4.1 Effect on Audio
        2. 8.3.4.2 Traditional Class-D Modulation Scheme
        3. 8.3.4.3 TPA2010D1 Modulation Scheme
        4. 8.3.4.4 Efficiency: Use a Filter With the Traditional Class-D Modulation Scheme
        5. 8.3.4.5 Effects of Applying a Square Wave into a Speaker
        6. 8.3.4.6 When to Use an Output Filter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Summing Input Signals with the TPA2010D1
        1. 8.4.1.1 Summing Two Differential Inputs
        2. 8.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
        3. 8.4.1.3 TPA2010D1 Summing Two Single-Ended Inputs
      2. 8.4.2 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPA200110D1 With Differential Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Resistors (RI)
          2. 9.2.1.2.2 Decoupling Capacitor (CS)
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TPA20010D1 With Differential Input and Input Capacitors
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Input Capacitors (CI)
        3. 9.2.2.3 Application Curves
      3. 9.2.3 TPA20010D1 with Single-Ended Input
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Decoupling Capacitors
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Board Layout
      1. 11.2.1 Component Location
      2. 11.2.2 Trace Width
    3. 11.3 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage In active mode –0.3 6 V
In SHUTDOWN mode
VI Input voltage –0.3 7 V
Continuous total power dissipation –0.3 VDD + 0.3 V
TA Operating free-air temperature See Dissipation Ratings °C
TJ Operating junction temperature –40 85 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds YZF 260 °C
YEF 235 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage 2.5 5.5 V
VIH High-level input voltage SHUTDOWN 1.3 VDD V
VIL Low-level input voltage SHUTDOWN 0 0.35 V
RI Input resistor Gain ≤ 20 V/V (26 dB) 15 kΩ
VIC Common mode input voltage range VDD = 2.5 V, 5.5 V, CMRR ≤ –49 dB 0.5 VDD – 0.8 V
TA Operating free-air temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) TPA2010D1 UNIT
YZF (DSBGA)
9 PINS
RθJA Junction-to-ambient thermal resistance 100.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.7 °C/W
RθJB Junction-to-board thermal resistance 24.7 °C/W
ψJT Junction-to-top characterization parameter 3.5 °C/W
ψJB Junction-to-board characterization parameter 24.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage
(measured differentially)		 VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V 1 25 mV
PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V –75 –55 dB
CMRR Common mode rejection ratio VDD = 2.5 V to 5.5 V, VIC = VDD / 2 to 0.5 V,
VIC = VDD / 2 to VDD – 0.8 V		 –68 –49 dB
|IIH| High-level input current VDD = 5.5 V, VI = 5.8 V 100 µA
|IIL| Low-level input current VDD = 5.5 V, VI = –0.3 V 5 µA
I(Q) Quiescent current VDD = 5.5 V, no load 3.4 4.9 mA
VDD = 3.6 V, no load 2.8
VDD = 2.5 V, no load 2.2 3.2
I(SD) Shutdown current V(SHUTDOWN) = 0.35 V, VDD = 2.5 V to 5.5 V 0.5 2 µA
rDS(on) Static drain-source on-state
resistance		 VDD = 2.5 V 700 mΩ
VDD = 3.6 V 500
VDD = 5.5 V 400
Output impedance in SHUTDOWN V(SHUTDOWN) = 0.35 V >1 kΩ
f(sw) Switching frequency VDD = 2.5 V to 5.5 V 200 250 300 kHz
Gain VDD = 2.5 V to 5.5 V
TPA2010D1 eq_min_los417.gif
TPA2010D1 eq_typ_los417.gif
TPA2010D1 eq_max_los417.gif
TPA2010D1 eq_unit_los417.gif
Resistance from shutdown to GND 300 kΩ

6.6 Operating Characteristics

TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power THD + N = 10%, f = 1 kHz, RL = 4 Ω VDD = 5 V 2.5 W
VDD = 3.6 V 1.3
VDD = 2.5 V 0.52
THD + N = 1%, f = 1 kHz, RL = 4 Ω VDD = 5 V 2.08 W
VDD = 3.6 V 1.06
VDD = 2.5 V 0.42
THD + N = 10%, f = 1 kHz, RL = 8 Ω VDD = 5 V 1.45 W
VDD = 3.6 V 0.73
VDD = 2.5 V 0.33
THD + N = 1%, f = 1 kHz, RL = 8 Ω VDD = 5 V 1.19 W
VDD = 3.6 V 0.59
VDD = 2.5 V 0.26
THD+N Total harmonic distortion plus
noise		 VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz 0.18%
VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz 0.19%
VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz 0.20%
kSVR Supply ripple rejection ratio VDD = 3.6 V, Inputs ac-grounded
with Ci = 2 µF		 f = 217 Hz,
V(RIPPLE) = 200 mVpp		 –67 dB
SNR Signal-to-noise ratio VDD = 5 V, PO = 1 W, RL = 8 Ω 97 dB
Vn Output voltage noise VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 µF		 No weighting 48 µVRMS
A weighting 36
CMRR Common mode rejection ratio VDD = 3.6 V, VIC = 1 Vpp f = 217 Hz –63 dB
ZI Input impedance 142 150 158 kΩ
Start-up time from shutdown VDD = 3.6 V 1 ms

6.7 Dissipation Ratings

PACKAGE DERATING FACTOR(1) TA ≤ 25°C
POWER RATING		 TA = 70°C
POWER RATING		 TA = 85°C
POWER RATING
YZF 7.8 mW/°C 780 mW 429 mW 312 mW
(1) Derating factor measure with High K board.

6.8 Typical Characteristics

TPA2010D1 tc_eff_los417.gif
Figure 1. Efficiency versus Output Power
TPA2010D1 tc_pow_los417.gif
Figure 3. Power Dissipation versus Output Power
TPA2010D1 tc_sup_los417.gif
Figure 5. Supply Current versus Output Power
TPA2010D1 tc_sup2_los417.gif
Figure 7. Supply Current versus Supply Voltage
TPA2010D1 tc_out_los417.gif
Figure 9. Output Power versus Load Resistance
TPA2010D1 tc_out2_los417.gif
Figure 11. Output Power versus Supply Voltage
TPA2010D1 tc_total1_los417.gif
Figure 13. Total Harmonic Distortion + Noise versus Output Power
TPA2010D1 tc_total3_los417.gif
Figure 15. Total Harmonic Distortion + Noise versus Frequency
TPA2010D1 tc_total5_los417.gif
Figure 17. Total Harmonic Distortion + Noise versus frequency
TPA2010D1 tc_supr_los417.gif
Figure 19. Supply Ripple Rejection Ratio versus Frequency
TPA2010D1 tc_supr2_los417.gif
Figure 21. Supply Ripple Rejection Ratio versus Frequency
TPA2010D1 tc_gsm1_los417.gif
Figure 23. GSM Power Supply Rejection versus Frequency
TPA2010D1 tc_com_los417.gif
Figure 25. Common-Mode Rejection Ratio versus
Frequency
TPA2010D1 tc_eff1_los417.gif
Figure 2. Efficiency versus Output Power
TPA2010D1 tc_pow1_los417.gif
Figure 4. Power Dissipation versus Output Power
TPA2010D1 tc_sup1_los417.gif
Figure 6. Supply Current versus Output Power
TPA2010D1 tc_shut_los417.gif
Figure 8. Supply Current versus Shutdown Voltage
TPA2010D1 tc_out1_los417.gif
Figure 10. Output Power versus Load Resistance
TPA2010D1 tc_total_los417.gif
Figure 12. Total Harmonic Distortion + Noise versus Output Power
TPA2010D1 tc_total2_los417.gif
Figure 14. Total Harmonic Distortion + Noise versus Frequency
TPA2010D1 tc_total4_los417.gif
Figure 16. Total Harmonic Distortion + Noise versus Frequency
TPA2010D1 tc_total6_los417.gif
Figure 18. Total Harmonic Distortion + Noise versus Common Mode Input Voltage
TPA2010D1 tc_supr1_los417.gif
Figure 20. Supply Ripple Rejection Ratio versus Frequency
TPA2010D1 tc_gsm_los417.gif
Figure 22. GSM Power Supply Rejection versus Time
TPA2010D1 tc_supr3_los417.gif
Figure 24. Supply Ripple Rejection Ratio versus DC Common Mode Voltage
TPA2010D1 tc_com1_los417.gif
Figure 26. Common-Mode Rejection Ratio versus
Common-Mode Input Voltage