SLASEM8A January   2019  – March 2019 TPA3255-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Total Harmonic Distortion
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Audio Characteristics (BTL)
    7. 6.7  Audio Characteristics (SE)
    8. 6.8  Audio Characteristics (PBTL)
    9. 6.9  Typical Characteristics, BTL Configuration
    10. 6.10 Typical Characteristics, SE Configuration
    11. 6.11 Typical Characteristics, PBTL Configuration
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Error Reporting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Protection System
        1. 8.4.1.1 Overload and Short Circuit Current Protection
        2. 8.4.1.2 Signal Clipping and Pulse Injector
        3. 8.4.1.3 DC Speaker Protection
        4. 8.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 8.4.1.5 Overtemperature Protection OTW and OTE
        6. 8.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 8.4.1.7 Fault Handling
        8. 8.4.1.8 Device Reset
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedures
          1. 9.2.1.2.1 Decoupling Capacitor Recommendations
          2. 9.2.1.2.2 PVDD Capacitor Recommendation
          3. 9.2.1.2.3 PCB Material Recommendation
          4. 9.2.1.2.4 Oscillator
      2. 9.2.2 Application Curves
      3. 9.2.3 Typical Application, Single Ended (1N) SE
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedures
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Typical Application, Differential (2N) PBTL
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedures
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
      1. 10.1.1 VDD Supply
      2. 10.1.2 GVDD_X Supply
      3. 10.1.3 PVDD Supply
    2. 10.2 Powering Up
    3. 10.3 Powering Down
    4. 10.4 Thermal Design
      1. 10.4.1 Thermal Performance
      2. 10.4.2 Thermal Performance with Continuous Output Power
      3. 10.4.3 Thermal Performance with Non-Continuous Output Power
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 BTL Application Printed Circuit Board Layout Example
      2. 11.2.2 SE Application Printed Circuit Board Layout Example
      3. 11.2.3 PBTL Application Printed Circuit Board Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

PVDD_X = 51 V, GVDD_X = 10.6 V, VDD = 10.6 V, TC (Case temperature) = 75°C, fS = 450 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
DVDD Voltage regulator, only used as reference node VDD = 10.6 V 3 3.3 3.6 V
AVDD Voltage regulator, only used as reference node VDD = 10.6 V 7.75 V
IVDD VDD supply current Operating, 50% duty cycle 30 mA
Idle, reset mode 14
IGVDD_X Gate-supply current per full-bridge 50% duty cycle 44 mA
Reset mode 5
IPVDD_X PVDD idle current per full bridge 50% duty cycle with recommended output filter 24 mA
Reset mode, No switching 5 mA
VDD = 0V, GVDD_X = 0V 1.25 mA
ANALOG INPUTS
RIN Input resistance 20 kΩ
VIN Maximum input voltage swing, peak - peak 7 V
IIN Maximum input current 1 mA
G Inverting voltage Gain VOUT/VIN 21.5 dB
OSCILLATOR
FPWM PWM Output Frequency Nominal, Master Mode, 1% Resistor 450 kHz
AM1, Master Mode, 1% Resistor 500
AM2, Master Mode, 1% Resistor 600
ΔFPWM PWM Output Frequency Variation 1% Resistor 5 %
fOSC(IO+) Oscillator Frequency Nominal, Master Mode, FPWM × 6 2.7 MHz
AM1, Master Mode, FPWM × 6 3
AM2, Master Mode, FPWM × 6 3.45 3.6 3.75
ΔfOSC(IO+) Oscillator Frequency Variation 5 %
VIH High level input voltage 1.86 V
VIL Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
RDS(on) Drain-to-source resistance, low side (LS) TJ = 25°C, Includes metallization resistance,
GVDD = 10.6 V		 85 mΩ
Drain-to-source resistance, high side (HS) 85 mΩ
I/O
PROTECTION
Vuvp,VDD,GVDD Undervoltage protection limit, GVDD_x and VDD 8.7 V
Vuvp,VDD, GVDD,hyst(1) 0.6 V
Vuvp,PVDD Undervoltage protection limit, PVDD_x 14.5 V
Vuvp,PVDD,hyst(1) 1.4 V
OTW Overtemperature warning, CLIP_OTW(1) 110 120 130 °C
OTWhyst(1) Temperature drop needed below OTW temperature for CLIP_OTW to be inactive after OTW event. 20 °C
OTE(1) Overtemperature error 140 150 160 °C
OTEhyst(1) A reset needs to occur for FAULT to be released following an OTE event 15 °C
OTE-OTW(differential)(1) OTE-OTW differential 30 °C
OLPC Overload protection counter fPWM = 450 kHz (1024 PWM cycles) 2.3 ms
IOC Overcurrent limit protection Resistor – programmable, nominal peak current in 1Ω load, ROCP = 22 kΩ 17 A
Resistor – programmable, nominal peak current in 1Ω load, ROCP = 30 kΩ 13
IOC(LATCHED) Overcurrent limit protection Resistor – programmable, peak current in 1Ω load, ROCP = 47kΩ 17 A
Resistor – programmable, peak current in 1Ω load, ROCP = 64kΩ 13
IDCspkr DC Speaker Protection Current Threshold BTL current imbalance threshold 1.5 A
IOCT Overcurrent response time Time from switching transition to flip-state induced by overcurrent. 150 ns
IPD Output pulldown current of each half Connected when RESET is active to provide bootstrap charge. Not used in SE mode. 3 mA
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage M1, M2, OSC_IOP, OSC_IOM, RESET 1.9 V
VIL Low level input voltage 0.8 V
Ilkg Input leakage current 100 μA
OTW/SHUTDOWN (FAULT)
RINT_PU Internal pullup resistance, CLIP_OTW to DVDD, FAULT to DVDD 26 kΩ
ΔRINT_PU Internal pullup resistance variation, CLIP_OTW to DVDD, FAULT to DVDD 25 %
VOH High level output voltage Internal pullup resistor 3 3.3 3.6 V
VOL Low level output voltage IO = 4 mA 10 500 mV
Device fanout CLIP_OTW, FAULT No external pullup 30 devices
(1) Specified by design.