SLASEM8A January   2019  – March 2019 TPA3255-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Total Harmonic Distortion
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Audio Characteristics (BTL)
    7. 6.7  Audio Characteristics (SE)
    8. 6.8  Audio Characteristics (PBTL)
    9. 6.9  Typical Characteristics, BTL Configuration
    10. 6.10 Typical Characteristics, SE Configuration
    11. 6.11 Typical Characteristics, PBTL Configuration
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Error Reporting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Protection System
        1. 8.4.1.1 Overload and Short Circuit Current Protection
        2. 8.4.1.2 Signal Clipping and Pulse Injector
        3. 8.4.1.3 DC Speaker Protection
        4. 8.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 8.4.1.5 Overtemperature Protection OTW and OTE
        6. 8.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 8.4.1.7 Fault Handling
        8. 8.4.1.8 Device Reset
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedures
          1. 9.2.1.2.1 Decoupling Capacitor Recommendations
          2. 9.2.1.2.2 PVDD Capacitor Recommendation
          3. 9.2.1.2.3 PCB Material Recommendation
          4. 9.2.1.2.4 Oscillator
      2. 9.2.2 Application Curves
      3. 9.2.3 Typical Application, Single Ended (1N) SE
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedures
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Typical Application, Differential (2N) PBTL
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedures
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
      1. 10.1.1 VDD Supply
      2. 10.1.2 GVDD_X Supply
      3. 10.1.3 PVDD Supply
    2. 10.2 Powering Up
    3. 10.3 Powering Down
    4. 10.4 Thermal Design
      1. 10.4.1 Thermal Performance
      2. 10.4.2 Thermal Performance with Continuous Output Power
      3. 10.4.3 Thermal Performance with Non-Continuous Output Power
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 BTL Application Printed Circuit Board Layout Example
      2. 11.2.2 SE Application Printed Circuit Board Layout Example
      3. 11.2.3 PBTL Application Printed Circuit Board Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.2.4 Oscillator

The built in oscillator frequency can be trimmed by an external resistor from the FREQ_ADJ pin to GND. Changes in the oscillator frequency should be made with resistor values specified in Recommended Operating Conditions while RESET is low.

To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency can be changed from nominal to lower or higher values. These values should be chosen such that the nominal and the alternate switching frequencies together result in the fewest cases of interference throughout the AM band. The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in master mode.

For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to DVDD. This configures the OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter-channel delay is automatically set up between the switching of the audio channels, which can be illustrated by no idle channels switching at the same time. This will not influence the audio output, but only the switch timing to minimize noise coupling between audio channels through the power supply. Inter-channel delay is needed to optimize audio performance and to get better operating conditions for the power supply. The inter-channel delay will be set up for a slave device depending on the polarity of the OSC_I/O connection as follows:

  • Slave 1 mode has normal polarity (master + to slave + and master - to slave -)
  • Slave 2 mode has reverse polarity (master + to slave - and master - to slave +)

The interchannel delay for interleaved channel idle switching is given in the table below for the master/slave and output configuration modes in degrees relative to the PWM frame.

Table 7. Master/Slave Inter Channel Delay Settings

Master M1 = 0, M2 = 0, 2 x BTL mode M1 = 1, M2 = 0, 1 x BTL + 2 x SE mode M1 = 0, M2 = 1, 1 x PBTL mode M1 = 1, M2 = 1, 4 x SE mode
OUT_A 0° 0° 0° 0°
OUT_B 180° 180° 180° 60°
OUT_C 60° 60° 0° 0°
OUT_D 240° 120° 180° 60°
Slave 1
OUT_A 60° 60° 60° 60°
OUT_B 240° 240° 240° 120°
OUT_C 120° 120° 60° 60°
OUT_D 300° 180° 240° 120°
Slave 2
OUT_A 30° 30° 30° 30°
OUT_B 210° 210° 210° 90°
OUT_C 90° 90° 30° 30°
OUT_D 270° 150° 210° 90°