SLVSAC2G August   2010  – June 2021 TPD2EUSB30 , TPD2EUSB30A , TPD4EUSB30

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on D+, D- Pins
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Typical Characteristics

GUID-34E03649-6077-42DA-BDCF-7AC249CE48FE-low.gif
TA = 25 °C
Figure 6-1 IO Capacitance vs IO Voltage
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Measured at one IO, the other IO open
Figure 6-3 Peak Pulse Waveforms
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Figure 6-5 IEC Clamping Waveforms (8 kV Contact)
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–3 dB = 7.4 Gbps
Figure 6-7 Insertion Loss
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VIO = 2.5 V
Figure 6-2 Leakage Current vs Temperature
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Figure 6-4 D+,D– Transmission Line Pulser Plot for TPD2EUSB30 (100 ns Pulse, 10 ns Rise Time)
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Figure 6-6 IEC Clamping Waveforms (–8 kV Contact)