Dual l 0.7-pF, 3.6-V, ±8-kV ESD protection diode with 5-A surge rating for USB 3.0
Product details
Parameters
Package | Pins | Size
Features
- Supports USB 3.0 Data Rates (5 Gbps)
- IEC 61000-4-2 ESD Protection (Level 4 Contact)
- IEC 61000-4-5 Surge Protection
- 5 A (8/20 µs)
- Low Capacitance
- DRT: 0.7 pF (Typ)
- DQA: 0.8 pF (Typ)
- Dynamic Resistance: 0.6 Ω (Typ)
- Space-Saving DRT, DQA Packages
- Flow-Through Pin Mapping
Description
The TPD2EUSB30, TPD2EUSB30A, and TPD4EUSB30 are 2 and 4 channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode arrays. The TPDxEUSB30/A devices are rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Contact). These devices also offer 5 A (8/20 µs) peak pulse current ratings per IEC 61000-4-5 (Surge) specification.
The TPD2EUSB30A offers low 4.5-V DC break-down voltage. The low capacitance, low break-down voltage, and low dynamic resistance make the TPD2EUSB30A a superior protection device for high-speed differential IOs.
The TPD2EUSB30 and TPD2EUSB30A are offered in space saving DRT (1 mm × 1 mm) package. The TPD4EUSB30 is offered in space saving DQA (2.5 mm × 1.0 mm) package.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | TPDxEUSB30 2-, 4-Channel ESD Protection for Super-Speed USB 3.0 Interface datasheet (Rev. F) | Oct. 13, 2015 |
User guide | Generic ESD Evaluation Module User's Guide | Apr. 03, 2018 | |
White paper | Designing USB for short-to-battery tolerance in automotive environments | Feb. 10, 2016 | |
Application note | ESD Layout Guide | Mar. 04, 2015 | |
Application note | Design Considerations for System-Level ESD Circuit Protection | Sep. 25, 2012 | |
Application note | Reading and Understanding an ESD Protection Datasheet | May 19, 2010 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Allows testing of most TI ESD devices
- Many footprints to allow testing of each part
- S-parameter testing for signal integrity
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download PMP40496 Assembly Drawing.pdf (322KB) -
download PMP40496 PCB.pdf (1341KB) -
download PMP40496 Gerber.zip (1242KB) -
download PMP40496 BOM (Rev. A).pdf (102KB) -
download PMP40496 CAD Files (Rev. A).zip (2510KB)
Design files
Design files
Design files
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOT-9X3 (DRT) | 3 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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