SLVSDG5C March   2016  – August 2020 TPD3S014-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics: TJ = TA = 25°C
    8. 6.8 Electrical Characteristics: –40°C ≤ TA ≤ 105°C
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable
      3. 8.3.3 Internal Charge Pump
      4. 8.3.4 Current Limit
      5. 8.3.5 Output Discharge
      6. 8.3.6 Input and Output Capacitance
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
      3. 8.4.3 Operation of Level 4 IEC 61000-4-2 ESD Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Implementing Active Low Logic
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation and Junction Temperature
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPD3S014-Q1. The system designer can control choices of the devices proximity to other power dissipating devices and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by system considerations. It is important to remember that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. In particular, connect the GND pin to a large ground plane for the best thermal dissipation. The following PCB layout example in Figure 11-2 was used to determine the RθJA Custom thermal impedances noted in the Thermal Information table. It is based on the use of the JEDEC high-k circuit board construction with 4, 1 oz. copper weight layers (2 signal and 2 plane).

GUID-549EE72B-A149-4EC5-993B-C853C640FB27-low.gif Figure 11-2 PCB Layout Example

The following procedure requires iteration a power loss is because of the internal MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. See Equation 1. As an initial estimate, use the RDS(ON) at 105°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred board construction from the Thermal Information table.

Equation 1. TJ = TA + [(IOUT2 × RDS(ON)) × RθJA]

where

  • IOUT = Rated OUT pin current (A)
  • RDS(ON) = Power switch on-resistance at an assumed TJ (Ω)
  • TA = Maximum ambient temperature (°C)
  • TJ = Maximum junction temperature (°C)
  • RθJA = Thermal resistance (°C/W)

If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using the typical characteristic plot and recalculate.

If the resulting TJ is not less than 125°C, try a PCB construction with a lower RθJA. The junction temperature derating curve based on the TI standard reliability duration is shown in Figure 11-3.

GUID-D1C04B5A-32B2-45B7-B623-682C8F043F0C-low.gif Figure 11-3 Junction Temperature Derating Curve