SLVSDG5C March   2016  – August 2020 TPD3S014-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics: TJ = TA = 25°C
    8. 6.8 Electrical Characteristics: –40°C ≤ TA ≤ 105°C
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable
      3. 8.3.3 Internal Charge Pump
      4. 8.3.4 Current Limit
      5. 8.3.5 Output Discharge
      6. 8.3.6 Input and Output Capacitance
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
      3. 8.4.3 Operation of Level 4 IEC 61000-4-2 ESD Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Implementing Active Low Logic
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation and Junction Temperature
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3 Implementing Active Low Logic

For active low logic, a transistor can be used with the TPD3S014-Q1 EN Pin. Figure 9-2 shows how to implement Active low logic for EN pin.

Using an nFET transistor, when the Processor sends a low signal, the transistor is switched off, and VLOGIC pulls up EN through R1. When the Processor sends a “high” signal, the nFET is switched on and sinks current from the EN Pin and R1. For 5 V VLOGIC, with the appropriate on-resistance (RON) value in the nFET and resistance for R1, the VIL for EN can be met. For example, with a transistor with RON of 3 Ω, a pull-up resistor as low as 11 Ω provides a logic level of 0.7 V. For power-budgeting concerns, a better choice is R1 of 40 kΩ which provides 0.25 V for EN when the Processor asserts high, and 4.96 V when the Processor asserts low.

GUID-2DF63767-A235-44A3-BE40-BFFA41A0C55F-low.gifFigure 9-2 Implementing Active Low Logic for EN Pin