SLLSEG0F March   2013  – September 2017 TPD4E001-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 AEC-Q100 Qualified
      2. 7.3.2 IEC 61000-4-2 Level 4 ESD Protection
      3. 7.3.3 IEC 61000-4-5 Surge Protection
      4. 7.3.4 Low 1.5-pF Input Capacitance
      5. 7.3.5 Low 10-nA (Maximum) Leakage Current
      6. 7.3.6 0.9-V to 5.5-V Supply Voltage Range
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Signal Range on IO1 Through IO4
        2. Voltage Range on VCC
        3. Bandwidth on IO1 Through IO4
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TPD4E001-Q1 device is a TVS diode array which is typically used to provide a path to ground for dissipating ESD events on high-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.

Typical Application

For this design example, one TPD4E001-Q1 device is being used in a dual USB 2.0 application. This provides a complete port protection scheme.

TPD4E001-Q1 appin_lls682.gif Figure 4. Typical Application Schematic

Design Requirements

For this design example, a single TPD4E001-Q1 device is used to protect all the pins on two USB2.0 connectors.

Given the USB application, known parameters are listed in the Table 1.

Table 1. Design Parameters

Signal range on IO1, IO2, IO3, or IO4 0 V to 3.6 V
Voltage range on VCC 0 V to 5.25 V
Operating Frequency on IO1, IO2, IO3, or IO4 240 MHz

Detailed Design Procedure

To begin the design process, some parameters must be decided upon; the designer needs to know the following:

  • Signal range on all protected lines
  • Operating frequency on all protected lines

Signal Range on IO1 Through IO4

The TPD4E001-Q1 device has 4 identical protection channels for signal lines. The symmetry of the device provides flexibility when selecting which of the 4 IO channels protects which signal lines. Any IO supports a signal range of 0 to (VCC + 0.3) V. Therefore, this device supports the USB 2.0 signal swing assuming VCC is set appropriately.

Voltage Range on VCC

The VCC pin can be connected in one of two ways:

  • If the VCC pin connects to the system power supply, the TPD4E001-Q1 device works as a transient suppressor for any signal swing above VCC + VF. TI recommends a 0.1-μF capacitor on the device VCC pin for ESD bypass.
  • If the VCC pin does not connect to the system power supply, the TPD4E001-Q1 device can tolerate higher signal swing in the range up to 10 V. Note that TI still recommends a 0.1-μF capacitor at the VCC pin for ESD bypass.

If this pin is connected to the USB 2.0 VBUS supply or left floating, the allowable signal swing is enough for a USB 2.0 application.

Bandwidth on IO1 Through IO4

Each IO pin on the TPD4E001-Q1 device has a typical capacitance of 1.5 pF. This capacitance is low enough to easily support USB 2.0 data rates.

Application Curve

TPD4E001-Q1 D001_SLLSEG0.gif Figure 5. IEC 61000-4-2 Voltage Clamp Waveform 8-kV Contact