SLLSEG0F March   2013  – September 2017 TPD4E001-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 AEC-Q100 Qualified
      2. 7.3.2 IEC 61000-4-2 Level 4 ESD Protection
      3. 7.3.3 IEC 61000-4-5 Surge Protection
      4. 7.3.4 Low 1.5-pF Input Capacitance
      5. 7.3.5 Low 10-nA (Maximum) Leakage Current
      6. 7.3.6 0.9-V to 5.5-V Supply Voltage Range
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Signal Range on IO1 Through IO4
        2. Voltage Range on VCC
        3. Bandwidth on IO1 Through IO4
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The TPD4E001-Q1 device is a low-capacitance, TVS diode array designed for ESD protection in sensitive electronics connected to communication lines. Each channel consists of a pair of transient voltage suppression diodes that steer ESD pulses to VCC or GND. The TPD4E001-Q1 device protects against ESD events up to ±8-kV contact discharge and ±15-kV air-gap discharge, as specified in IEC 61000-4-2 international standard. This device has a low capacitance of 1.5-pF per channel making it ideal for use in high-speed data interfaces. The low-leakage current (10 nA maximum) ensures minimum power consumption for the system and high accuracy for analog interfaces.

Functional Block Diagram

TPD4E001-Q1 lb_lls682.gif

Feature Description

AEC-Q100 Qualified

This device is qualified according to the AEC-Q100 standard. The device temperature rating is Grade 1 (–40°C to +125°C). The HBM Classification Level passed is 3B (> 8 kV). The CDM Classification Level passed is C5 (all pins 750 V to <1000 V).

IEC 61000-4-2 Level 4 ESD Protection

The device is specified at ±8-kV contact discharge and ±15-kV air gap discharge.

IEC 61000-4-5 Surge Protection

This device is rated to pass at least 5.5-A of peak pulse current according to the IEC 61000-4-5 (8/20-µs pulse) standard.

Low 1.5-pF Input Capacitance

This device has a typical capacitance of 1.5-pF on each of the four IO pins. This allows for high speed signals on the IO pins in excess of 1 Gbps.

Low 10-nA (Maximum) Leakage Current

This device is rated to have a maximum leakage current of 10-nA on each of the four IO pins.

0.9-V to 5.5-V Supply Voltage Range

This device is specified to operate with a supply voltage (on VCC) between 0.9-V and 5.5-V to ensure sufficient signal integrity.

Device Functional Modes

The TPD4E001-Q1 device is a passive integrated circuit that triggers when voltages are above VBR or below the lower diodes VF (–0.6 V). During ESD events, voltages as high as ±8 kV (contact) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD4E001-Q1 (usually within 10s of nano-seconds) the device reverts back to its high-impedance state.