SLVSBO7N December   2012  – February 2022 TPD1E05U06 , TPD4E05U06 , TPD6E05U06

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1.     Absolute Maximum Ratings
    2. 6.1 ESD Ratings—JEDEC Specification
    3. 6.2 ESD Ratings—IEC Specification
    4.     Recommended Operating Conditions
    5. 6.3 Thermal Information
    6. 6.4 Electrical Characteristics
    7. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ±15-kV IEC61000-4-2 Level 4 ESD Protection
      2. 7.3.2 IEC61000-4-4 EFT Protection
      3. 7.3.3 IEC61000-4-5 Surge Protection
      4. 7.3.4 I/O Capacitance
      5. 7.3.5 DC Breakdown Voltage
      6. 7.3.6 Ultra-Low Leakage Current
      7. 7.3.7 Low ESD Clamping Voltage
      8. 7.3.8 Industrial Temperature Range
      9. 7.3.9 Easy Flow-Through Routing
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 HDMI 2.0 Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Signal Range on Pin 1, 2, 4, or 5
        3. 8.2.1.3 Application Curves
      2. 8.2.2 HDMI 2.0 Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Signal Range
          2. 8.2.2.2.2 Operating Frequency
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 TPD4E05U06 Layout Example
      2. 10.2.2 TPD1E05U06 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
INPUT - OUTPUT RESISTANCE
VRWM Reverse stand-off voltage IIO < 10 µA 5.5 V
VBR Break-down voltage IIO = 1 mA 6.5 8.5 V
VClamp Clamp voltage IPP = 1 A, TLP, from I/O to GND (1) 10 V
IPP = 5 A, TLP, from I/O to GND (1) 14
IPP = 1 A, TLP, from GND to I/O (1) 3
IPP = 5 A, TLP, from GND to I/O (1) 7
ILEAK Leakage current VIO = 2.5 V 0.01 10 nA
RDYN Dynamic resistance DPY package I/O to GND (2) 0.8 Ω
GND to I/O (2) 0.8
DYA package I/O to GND (2) 0.8
GND to I/O (2) 0.7
DQA package I/O to GND (2) 0.8
GND to I/O (2) 0.8
RVZ package I/O to GND (2) 0.8
GND to I/O (2) 0.8
CAPACITANCE
CL Line capacitance (3) VIO = 2.5 V;  ƒ = 1 MHz , I/O to GND TPD1E05U06 DPY
package		 0.42 pF
TPD1E05U06 DYA
package		 0.42
TPD4E05U06 DQA
package		 0.5
TPD6E05U06 RVZ
package		 0.47
Δ CIO-TO-GND Variation of input capacitance GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Channel x pin to GND – channel y pin to GND		 0.05 0.07 pF
CCROSS Channel to channel input capacitance GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V, between channel pins 0.01 0.06 pF
(1) Transition line pulse with 100 ns width, 200 ps rise time.
(2) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A.
(3) Capacitance data is taken at 25°C.