SLVSIF2 July   2025 TPD4S201

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 28-VDC Tolerant
      2. 6.3.2 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      3. 6.3.3 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VBIAS Capacitor Selection
        2. 7.2.2.2 Dead Battery Operation
        3. 7.2.2.3 CC Line Capacitance
        4. 7.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 7.2.2.5 FLT Pin Operation
        6. 7.2.2.6 How to Connect Unused Pins
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.4 Additional ESD Protection on CC and SBU Lines

If additional IEC ESD protection is desired to be placed on either the CC or SBU lines, it is important that high-voltage ESD protection diodes be used. The maximum DC voltage sensed on the CC or SBU lines in USB PD SPR is 21V, with 21.5V allowed during voltage transitions. To prevent the diode from breaking down during a short-to-VBUS event, use an ESD protection diode that has a reverse stand off voltage higher than 21.5V.

The short-to-VBUS event applies a DC voltage to the CC and SBU pins, do not use a deep-snap-back diode unless its minimum trigger voltage is above 42V. During a short-to-VBUS event, RLC ringing of up to twice the settling voltage is exposed to CC and SBU, allowing for up to 42V to be exposed to the CC and SBU lines. Greater ringing can occur if any capacitor derates on the CC or SBU line. Since this ringing is hard to bound, it is recommended to not use deep-snap-back diodes. If the deep-snap-back diode triggers during the short-to-VBUS hot-plug event, it begins to operate in its conduction region. With a 21V VBUS source present on the CC or SBU line, this allows the diode to conduct indefinitely.