SLVSBQ6B December   2012  – September 2015 TPD5E003

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6  Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: JEDEC
    3. 6.3 ESD Ratings: IEC 61000-4-2
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
I/O voltage tolerance 5.5 V
Peak pulse current (tp = 8/20 μs), IPP 3 A
Peak pulse power (tp = 8/20 μs), PPP 40 W
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings: JEDEC

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings: IEC 61000-4-2

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±15000 V
IEC 61000-4-2 air-gap discharge ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Operating free-air temperature, TA –40 125 °C
Operating voltage Pin 1, 3, 4, 5, 6 to Pin 2 0 5 V

6.5 Thermal Information

THERMAL METRIC(1) TPD5E003 UNIT
DPF (X2SON)
6 PINS
RθJA Junction-to-ambient thermal resistance 246.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 87.8 °C/W
RθJB Junction-to-board thermal resistance 187.1 °C/W
ψJT Junction-to-top characterization parameter 2.6 °C/W
ψJB Junction-to-board characterization parameter 198 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 32 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT
VRWM Reverse stand-off voltage II = 0.1 µA 5 V
ILEAK Leakage Current Pin 1, 3, 4, 5, or 6 = 5 V, Pin 2 = 0 V 10 100 nA
VCLAMP Clamp voltage with ESD strike IPP = 6 A, TLP, Dx pin to GND, TA = 25 °C 13 15.6 V
IPP = 10 A, TLP, Dx pin to GND, TA = 25 °C 16.3 19.5 V
RDYN Dynamic resistance ITLP = 6 A to 10 A, Dx pin to GND, TA = 25 °C 0.8 1 Ω
ITLP = 6 A to 10 A, GND to Dx pin, TA = 25 °C 0.3 0.4 Ω
CIO IO capacitance VIO = 2.5 V, 1 MHz, TA = 25 °C 5.6 7 8.4 pF
VIO = 0 V, 1 MHz, TA = 25 °C 8 10 12 pF
VBR Break-down voltage IIO = 1 mA 6 7 8.5 V

6.7 Typical Characteristics

TPD5E003 C002_SLVSBQ6.png Figure 1. Surge Plot (tp = 8/20 μs), Pin Dx to GND
TPD5E003 C001_SLVSBQ6.png Figure 3. Capacitance vs DC Bias Voltage
TPD5E003 C005_SLVSBQ6.png Figure 5. DC SWEEP V-I Curve
TPD5E003 C007_SLVSBQ6.png Figure 7. IEC 61000-4-2 Clamping Voltage, –8-kV Contact
TPD5E003 C003_SLVSBQ6.png Figure 2. Surge Plot (tp = 8/20 μs), Pin GND to Dx
TPD5E003 C004_SLVSBQ6.png Figure 4. 30 A TLP Plot
TPD5E003 C006_SLVSBQ6.png Figure 6. IEC 61000-4-2 Clamping Voltage, 8-kV Contact