SLLSE33E August   2010  – December 2016 TPD7S019

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RSV Package
16-Pin UQFN
Top View
TPD7S019 po_rsv_llse33.gif
DBQ Package
16-Pin SSOP
Top View
TPD7S019 po_dbq_llse33.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME DBQ RSV
BYP 8 6 Power Bypass pin. Using a 0.2-µF bypass capacitor increases the ESD robustness of the system
DDC_IN1 10 8 I DDC signal input. Connects to the VGA controller side of one of the sync lines
DDC_IN2 11 9
DDC_OUT1 9 7 O DDC signal output. Connects to the video connector side of one of the sync lines
DDC_OUT2 12 10
GND 6 4 — Ground
SYNC_IN1 13 11 I Sync signal buffer input. Connects to the VGA controller side of one of the sync lines
SYNC_IN2 15 13
SYNC_OUT1 14 12 O Sync signal buffer output. Connects to the video connector side of one of the sync lines
SYNC_OUT2 16 14
VCC_DDC 7 5 Power Isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates
VCC_SYNC 1 15 Power Isolated supply input for the SYNC_1 and SYNC_2 level-shifters and their associated ESD protection circuits
VCC_VIDEO 2 16 Power Supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits
VIDEO1 3 1 ESD High-speed ESD clamp input
VIDEO2 4 2
VIDEO3 5 3