SLIS136C September   2011  – September 2019 TPL0501-100

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics: Analog Specifications
    5. 6.5 Electrical Characteristics: Operating Specifications
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Single-Channel, 256-Position Resolution
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage Divider Mode
      2. 7.4.2 Rheostat Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Digital Interface
        1. Table 1. Register Map - Default Value 0x80
      2. 7.5.2 Ideal Resistance Values
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequence
    2. 9.2 Wiper Position Upon Power Up
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Thermal Information

THERMAL METRIC(1) TPL0501 UNIT
DCN (SOT-23) RSE (UQFN)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance(2) 205.6 118.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 122.3 62.4 °C/W
RθJB Junction-to-board thermal resistance 98.9 26.8 °C/W
ψJT Junction-to-top characterization parameter 38.7 2.3 °C/W
ψJB Junction-to-board characterization parameter 97.8 26.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.