SNAS628B JULY   2013  – December 2014 TPL5000

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Application Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Ratings
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Supervisor Feature
        1. 8.3.1.1 Calibration Pulse
        2. 8.3.1.2 Overview of the Timing Signals: WAKE, RSTN, TCAL and DONE
        3. 8.3.1.3 Watchdog Feature
        4. 8.3.1.4 Different Utilizations of the TPL5000
      2. 8.3.2 Configuration and Interface
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPL5000 is a long-term timer with a watchdog feature for low-power applications. The TPL5000 is designed for use in interrupt-driven applications and provides selectable timing from 1 s to 64 s. An additional supervisor feature is achieved through interfacing the TPL5000 to a power-management IC.

8.2 Functional Block Diagram

BLOCK_DIAGRAM.gif

8.3 Feature Description

8.3.1 Supervisor Feature

A critical event that can corrupt the memory of a microcontroller is a voltage supply drop (supply lower than minimum operating range), and a reset of the microcontroller is mandatory if this occurs. Since the TPL5000 is the right choice in systems which stay most of the time in deep sleep, due to its ultra-low power consumption, it is fundamental that it takes into account the voltage drop events.

The TPL5000 implements a supervisory functionality when working with some power-management ICs which indicate the status of the supply voltage with a power-good or battery-good output. The supervisory functionality is enabled by simply connecting the Battery management power-good output to the TPL5000 PGOOD pin. If this feature is not used connect the PGOOD pin to VDD.

In case the power management IC detects a voltage drop, lowering the PGOOD line, while the microcontroller is in deep sleep mode (in which internal supervisors are usually off), the TPL5000 internally latches that event, and when the PGOOD returns to high, it sends out a RESET signal to the microcontroller at the end of the elapsed delay period.

Figure 6 shows the supervisor feature of the TPL5000. The sequence F, G is a standard sequence where the microcontroller is in deep sleep and a voltage supply drop occurs (which is highlighted by the PGOOD high to low transition). When PGOOD is high again, a reset pulse at the end of the delay period is sent to the microcontroller (arrow F), then the microcontroller executes its routine (memory has been reloaded upon reset) and sends the "DONE" signal.

Timing_watchdog.gifFigure 6. Watchdog and Supervisor Feature

8.3.1.1 Calibration Pulse

The TPL5000 is based on a ultra-low power oscillator which has a relatively low frequency and low accuracy; however, it shows very good cycle-to-cycle repeatability and very low temperature drift. In most of the applications, the accuracy of the oscillator is enough, but if a more accurate measure of the delay period is required, it is possible to measure the base period of the internal oscillator. A single pulse, which has the same duration as the base period of the internal oscillator, is present at the TCAL pin of the TPL5000. This pulse starts after a half period of the internal oscillator from either the falling edge of the RESET pulse, or the rising edge of the WAKE pulse.

A microcontroller connected to the TPL5000 can routinely measure the width of the TCAL pulse using a counter and an external crystal. Once the base period of the TPL5000 is measured, the actual time delay is calculated by multiplying the measured period by a factor, N (see Table 1), dependent on the nominal selected time delay.

The resolution and the accuracy of the measurement depend on the external crystal. Since the frequency of the internal oscillator of the TPL5000 is very stable, the measurement of the calibration pulse is suggested only when a high gradient of ambient temperature is observed. The measurement of the TCAL pulse is useful in battery-powered applications that implement a precise battery life counter in the microcontroller.

8.3.1.2 Overview of the Timing Signals: WAKE, RSTN, TCAL and DONE

Figure 7 shows the timing of WAKE, RSTn, and TCAL with respect to DONE. The frame, A, shows a typical sequence after the PGOOD, low to high, transition. As soon as PGOOD is high, the internal oscillator is powered ON. At the end of the delay period (tDP), a reset signal (RSTn), followed by a calibration pulse, TCAL, is sent out. The calibration pulse starts after a half period of the internal oscillator from the falling edge of the reset, and lasts one internal oscillator period.

The frame, B, shows a standard sequence. A "DONE" signal has been received in the previous delay period, so at the end of the next delay period, a "WAKE", followed by a calibration pulse, is sent out. The WAKE signal stays high for 2 internal oscillator periods. The calibration pulse starts after a half period of the internal oscillator from the rising edge of the WAKE signal, and lasts one internal oscillator period. In this frame, the TPL5000 receives a "DONE" signal before the end of the delay period.

The frame, C, still shows a standard sequence, but in this case, the TPL5000 receives the DONE signal when both WAKE and TCAL pulses are still high. As soon as the TPL5000 recognizes the DONE resets the counter and puts WAKE and TCAL in the default condition (both signal low).

The frame, D, shows a typical PGOOD, high to low transition. As soon as PGOOD is low, the internal oscillator is powered OFF and the digital output pins, TCAL, RSTn, and WAKE, are asynchronously reset by the falling edge of the PGOOD signal, such that TCAL and WAKE reset at low logical values, while RSTn resets at a high logical value.

Timing_signals.gifFigure 7. Timing PGOOD, WAKE, RSTN, TCAL

8.3.1.3 Watchdog Feature

Most of the microcontroller-based systems need to be self-reliant; if the software hangs for any reason, the microcontroller must be reset. The TPL5000 can provide this functionality by connecting a microcontroller programmable output pin to the DONE input pin. If the DONE line does not toggle within the selected delay period, then the microcontroller is not operating properly and must be reset.

The TPL5000 recognizes a valid DONE signal as a low to high transition; if two DONE signals are received within the delay period the second signal is ignored.

In the TPL5000, the watchdog window and the delay period are equivalent. A valid "DONE" signal resets the watchdog counter only, and not the delay time counter. A PGOOD low to high transition clears both the watchdog and delay time counters.

Figure 6 shows the watchdog feature of the TPL5000. The sequence A, B, C is a standard sequence with the microcontroller working properly. In this normal sequence, the microcontroller sends a valid "DONE" (arrow B) before the end of the delay period. The sequence C, D ,E is an anomalous sequence in which the microcontroller is not in a valid state, and it does not send the DONE signal (dashed pulse) before the end of the delay period. The TPL5000 determines the microcontroller is hung and sends a RESET signal (arrow E) when the period delay has elapsed.

8.3.1.4 Different Utilizations of the TPL5000

When either the watchdog or the supervisor feature of the TPL5000 are not required, it is possible to disable them reducing the interconnections between the TPL5000 and the microcontroller.

Connecting the DONE pin either to GND or to TCAL pin disables the watchdog feature. If connected to GND, the TPL5000 only sends a reset pulse when the time delay elapses. If DONE is connected to TCAL, the TPL5000 sends out just one RESET pulse after a PGOOD low to high transition, when the time delay elapses and then WAKE pulses when the successive time delay elapses.

Connecting the PGOOD pin to the supply pin of the TPL5000 disables the supervisor feature.

8.3.2 Configuration and Interface

The time interval between 2 adjacent WAKE pulses (or 2 adjacent RSTn pulses or RSTn and WAKE pulses) is selectable through 3 digital input pins (D0, D1, D2). These pins can be strapped to either VDD (1) or GND (0). Eight possible time delays can be selected, as shown in Table 1.

Table 1. Timer Delay Period

D2 D1 D0 Time (s) Factor N
0 0 0 1 26
0 0 1 2 27
0 1 0 4 28
0 1 1 8 29
1 0 0 10 10*26
1 0 1 16 210
1 1 0 32 211
1 1 1 64 212

8.4 Device Functional Modes

The TPL5000 mode of operations are selected through the PGOOD pin. There are two factors to consider when the PGOOD pin is at a high-logic level or low-logic level. When the PGOOD pin is at a high-logic level, the TPL5000 works as a timer and conversely at a low-logic level the TLP5000 does not work as a timer. For best use of TPL5000 waiting for high-logic is necessary.