SNAS628B JULY 2013 – December 2014 TPL5000
The more sensitive pins of the TPL5000 are the digital input pins D0, D1, D2 to select the timer interval. It is mandatory to connect them to VDD or GND through short traces avoiding series resistance. It is mandatory to keep these pins far from traces of high frequency signals, such as clock or communication bus. Signal integrity of WAKE, RSTn and TCAL signal is achieved reducing parasitic capacitance on the traces between the TPL5000 and the micro-controller. In the application where the watchdog feature is not used, the DONE pin is required to be tied to TCAL pin.