SLVSCG3F January 2014 – July 2017 TPS22968
To increase the current capabilities and lower the RON by approximately 50%, both channels can be placed in parallel as shown in Figure 31 (parallel configuration). With this configuration, the CT1 and CT2 pins can be tied together to use one capacitor, CT, as shown in Figure 31. With a single CT capacitor, the rise time is half of the typical rise-time value. Refer to the Table 1 for typical timing values.