SLVS841F November 2008 – August 2016 TPS2552 , TPS2552-1 , TPS2553 , TPS2553-1

PRODUCTION DATA.

- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information

- DRV|6

A SPH has a local power supply that powers embedded functions and downstream ports. This power supply must provide between 4.75 V to 5.25 V to downstream facing devices under full-load and no-load conditions. SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.

A BPH obtains all power from an upstream port and often contains an embedded function. It must power up with less than 100 mA. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, keep the power to the embedded function off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power-switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than 100 mA. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 µF at power up, the device must implement inrush current limiting.

The low ON-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It is good design practice to estimate power dissipation and junction temperature. The below analysis gives an approximation for calculating junction temperature based on the power dissipation in the package. However, it is important to note that thermal analysis is strongly dependent on additional system level factors. Such factors include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating power. Good thermal design practice must include all system level factors in addition to individual component analysis.

Begin by determining the r_{DS(on)} of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r_{DS(on)} from the typical characteristics graph. Using this value, the power dissipation can be calculated using Equation 7.

Equation 7. P_{D} = r_{DS(on)} × I_{OUT} ^{2}

where

- P
_{D}= Total power dissipation (W) - r
_{DS(on)}= Power switch on-resistance (Ω) - I
_{OUT}= Maximum current-limit threshold (A) - This step calculates the total power dissipation of the N-channel MOSFET.

Finally, calculate the junction temperature:

Equation 8. T_{J} = P_{D} × θ_{JA} + T_{A}

where

- T
_{A}= Ambient temperature (°C) - θ
_{JA}= Thermal resistance (°C/W) - P
_{D}= Total power dissipation (W)

Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat the calculation using the *refined* r_{DS(on)} from the previous calculation as the new estimate. Two or three iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent on thermal resistance θ_{JA}, and thermal resistance is highly dependent on the individual package and board layout. The *Thermal Information* table provides example thermal resistances for specific packages and board layouts.