SLVSCE1C August   2014  – November 2015 TPS25921A , TPS25921L


  1. Features
  2. Applications
  3. Description
  4. Application Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Characteristics
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Parametric Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable and Adjusting Undervoltage Lockout (UVLO)
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Hot Plug-in and In-Rush Current Control
      4. 9.3.4 Overload and Short Circuit Protection :
        1. Overload Protection
        2. Short Circuit Protection
        3. Start-Up with Short on Output
        4. Constant Current Limit Behavior during Overcurrent Faults
      5. 9.3.5 FAULT Response
      6. 9.3.6 IN, OUT and GND Pins
      7. 9.3.7 Thermal Shutdown:
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Control
      2. 9.4.2 Operational Overview of Device Functions
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Precision Current Limiting and Protection for White Goods
        1. Design Requirements
        2. Detailed Design Procedure
          1. Step by Step Design Procedure
          2. Programming the Current-Limit Threshold: R(ILIM) Selection
          3. Undervoltage Lockout and Overvoltage Set Point
          4. Setting Output Voltage Ramp time (tSS)
            1. Case1: Start-up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-up
            2. Case 2: Start-up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-up
          5. Support Component Selections - R4 and CIN
        3. Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Protection and Current Limiting for Primary-Side Regulated Power Supplies
      2. 10.3.2 Precision Current Limiting in Intrinsic Safety Applications
      3. 10.3.3 Smart Load Switch
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

  • For all applications, a 0.01-uF or greater ceramic decoupling capacitor is recommended between IN terminal and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be eliminated/minimized.
  • The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC. See Figure 52 for a PCB layout example.
  • High current carrying power path connections should be as short as possible and should be sized to carry at least twice the full-load current.
  • The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground should be a copper plane or island on the board.
  • Locate all TPS25921x support components: R(ILIM), CSS, and resistors for FLT, ENUV and OVP, close to their connection pin. Connect the other end of the component to the GND pin of the device with shortest trace length.
  • The trace routing for the RILIM and CSS components to the device should be as short as possible to reduce parasitic effects on the current limit and soft start timing. These traces should not have any coupling to switching signals on the board.
  • OVP and ENUV signal traces should be routed with sufficient spacing from FLT signal trace, to avoid spurious coupling of FLT switching, during fault conditions.
  • Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the device they are intended to protect, and routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads, and it should be physically close to the OUT pins.
  • Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been shown to produce good results and is intended as a guideline.

12.2 Layout Example

TPS25921A TPS25921L Layout_Diagram_slvsce1.gif
1. Optional: Needed only to suppress the transients caused by inductive load switching.
Figure 52. Board Layout