SLVSBR5C December   2012  – June  2015 TPS27082L


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
      1. 6.7.1 PFET Q1 Minimum Safe Operating Area (SOA)
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 ON/OFF
      2. 7.4.2 Fastest Output Rise Time
      3. 7.4.3 Controlled Output Rise Time
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Configuring Q1 ON-Resistance
        2. Configuring Turnon Slew Rate
        3. Configuring Turnoff Delay
        4. OFF Isolation Under VIN Transients
        5. Low Voltage ON/OFF Interface
        6. On-Chip Power Dissipation
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 TFT LCD Module Inrush Current Control
      2. 8.3.2 Standby Power Isolation
      3. 8.3.3 Boost Regulator With True Shutdown
      4. 8.3.4 Single Module Multiple Power Supply Sequencing
      5. 8.3.5 Multiple Modules Interdependent Power Supply Sequencing
      6. 8.3.6 Multiple Modules Interdependent Supply Sequencing Without a GPIO Input
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Improving Package Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS27082L IC is a high side load switch that integrates a Power PFET and a Control NMOS in a tiny package. The TPS27082L internal components are rated for up to 8V supply and support up to 3A of load current.

8.2 Typical Application

The TPS27082L can be used in a variety applications. Figure 15 shows a general application of TPS27082L to control the load inrush current. This section will highlight some of the design considerations when implementing this device in various applications.

TPS27082L typ_lvsbr5.gifFigure 15. Typical Application Diagram

8.2.1 Design Requirements

Add an external pullup resistor R1 between VIN and R1/C1 to control the ON-resistance of the load switch. Guidelines for sizing R1 can be found in Configuring Q1 ON-Resistance. In addition, TI recommends an output capacitor at VOUT to minimize the impact of inrush current from instantaneous switching. See Configuring Turnon Slew Rate for details regarding capacitor sizing.

8.2.2 Detailed Design Procedure Configuring Q1 ON-Resistance

VGS-Q1, Gate-Source voltage, of PMOS transistor Q1 sets its ON-resistance RQ1(ON). Connecting a high value pull up resistor R1 maximizes ON-state VGS-Q1 and thus minimizes the VIN to VOUT voltage drop. Use the following equation for calculating VGS-Q1:

Equation 1. TPS27082L Eq1_vgsq1_lvsbr5.gif

For example, R1= 125 kΩ, VIN = 5 V sets VGSQ1 = –4.5 V


It is recommended to keep R1 ≥ 125 kΩ. Higher value resistor R1 reduces ON-state quiescent current, increases turn-OFF delay, while reducing ON/OFF negative going threshold voltage VT–. Configuring Turnon Slew Rate

Switching a large capacitive load CL instantaneously results in a load inrush current given by the following equation:

Equation 2. TPS27082L Eq2_Iinrush_lvsbr5.gif

An uncontrolled fast rising ON/OFF logic input may result in a high slew rate (dv/dt)at the output thus leading to a higher load inrush current. To control the inrush current connect a capacitor C1 as shown in the Figure 15. Use the following approximate empirical equation to configure the TPS27082L slew rate to a specific value.

Equation 3. TPS27082L Eq3_trise_lvsbr5.gif


  • Trise is the time delta starting from the ON/OFF signal’s rising edge to charge up the load capacitor CL from 10% to 90% of VIN voltage

Table 1. Capacitor C1 Selection for Standard Output Rise Time

C1 (F)
R1 = 125 kΩ
VIN=7V VIN=5V VIN=3.3V VIN=1.8V VIN=1.2V
5 0 0 0 0 0
50 3.46n 2.77n 2.10n 1.41n 1.08n
100 6.91n 5.54n 4.21n 2.82n 2.16n
250 17.3n 13.8n 10.5n 7.05n 5.40n
470 32.5n 26.0n 19.8n 13.3n 10.1n
1000 69.1n 55.4n 42.1n 28.2n 21.6n


The trise equation and the capacitor C1 values recommended in the table above are under typical conditions and are accurate to within ±20%. Ensure R1 > 125kΩ; and select a closest standard valued capacitor C1. Configuring Turnoff Delay

TPS27082L PMOS turnoff delay from the falling edge of ON/OFF logic signal depends upon the component values of resistor R1 and capacitor C1. Lower values of resistor R1 ensures quicker turnoff.

Equation 4. toff > (R1 × C1 sec) OFF Isolation Under VIN Transients

TPS27082L architecture helps isolate fast transients at the VIN when PFET is in the OFF state. Best transient isolation is achieved when an external capacitor C1 is not connected across VOUT and R1/C1 pins. When a capacitor C1 is present the VIN to VOUT coupling is capacitive and is set by the C1 to CL capacitance ratio. TPS27082L architecture prevents direct conduction through PFET. Low Voltage ON/OFF Interface

To turn on the load switch apply a voltage > 1.0 V at the ON/OFF pin. The TPS27082L features hysteresis at its ON/OFF input. The turnon and turnoff thresholds are dependent upon the value of resistor R1. Refer to the Electrical Characteristics table and Figure 14 for details on the positive and negative going ON/OFF thresholds.

In applications where ON/OFF signal is not available connect ON/OFF pin to the VIN pin. The TPS27082L will turn ON and OFF in sync with the input supply connected to VIN. On-Chip Power Dissipation

Use below approximate equation to calculate TPS27082L’s on-chip power dissipation PD:

Equation 5. PD = IDQ12 × RQ1(ON)


  • IDQ1 is the DC current flowing through the transistor Q1

Refer to Electrical Characteristics table and the Figure 1 through Figure 7 to estimate RQ1(ON) for various values of VGSQ1.

Note: MOS switches can get extremely hot when operated in saturation region. As a general guideline, to avoid transistors Q1 going into saturation region set VGS > VDS + 1.0 V. E.g. VGS > 1.5 V and VDS < 200mV ensures switching region.

8.2.3 Application Curve

TPS27082L G008_lvsbr5.gifFigure 16. VIN Pin Leakage Current

8.3 System Examples

8.3.1 TFT LCD Module Inrush Current Control

TPS27082L app_ex_lvsbr5.gifFigure 17. Inrush Current Control Using TPS27082L

LCD panels require inrush current control to prevent permanent system damages during turn-ON and turn-OFF events.

8.3.2 Standby Power Isolation

TPS27082L stby_iso_lvsbr5.gifFigure 18. Boost

Many applications have some always ON modules to support various core functions. However, some modules are selectively powered ON or OFF to save power and multiplexing of various on board resources. Such modules that are selectively turned ON or OFF require standby power generation. In such applications TPS27082L requires only a single pull-up resistor. In this configuration the VOUT voltage rise time is approximately 250ns when VIN = 5V.

8.3.3 Boost Regulator With True Shutdown

TPS27082L boost_reg_lvsbr5.gifFigure 19. True Shutdown Using TPS27082L

The most common boost regulator topology provides a current leakage path through inductor and diode into the feedback resistor even when the regulator is shut down. Adding a TPS27082L in the input side power path prevents this leakage current and thus providing a true shutdown.

8.3.4 Single Module Multiple Power Supply Sequencing

TPS27082L multi_pwr_lvsbr5.gifFigure 20. Power Sequencing Using TPS27082L, Example 1

Most modern SOCs and CPUs require multiple voltage inputs for its Analog, Digital cores and IO interfaces. These ICs require that these supplies be applied simultaneously or in a certain sequence. TPS27082L when configured, as shown in Figure 20, with the VOUT1 rise time adjusted appropriately through resistor R2 and capacitor C1, will delay the early arriving LDO output to match up with late arriving DC-DC output and thus achieving power sequencing.

8.3.5 Multiple Modules Interdependent Power Supply Sequencing

TPS27082L multi_mod_lvsbr5.gifFigure 21. Power Sequencing Using TPS27082L, Example 2

For system integrity reasons a certain power sequencing may be required among various modules. As shown in Figure 21, Module 2 will power up only after Module 1 is powered up and the Module 1 GPIO output is enabled to turn ON Module 2. TPS27082L when used as shown in Figure 21 will not only sequence the Module 2 power, but also it will help prevent inrush current into the power path of Module 1 and 2.

8.3.6 Multiple Modules Interdependent Supply Sequencing Without a GPIO Input

TPS27082L multi_GPIO_lvsbr5.gifFigure 22. Power Sequencing using TPS27082L, Example 3

When a GPIO signal is not available connecting the ON/OFF pin of TPS27082 connected to Module 2 will power up Module 2 after Module 1, when resistor R4 and capacitor C1 are chosen appropriately. The two TPS27082L in this configuration will also control load inrush current.