SBVS050M May   2004  – March 2023 TPS3808

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Voltage Thresholds
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
      2. 8.3.2 Selecting the RESET Delay Time
      3. 8.3.3 Manual RESET ( MR) Input
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Immunity to SENSE Pin Voltage Transients
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Modules
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-448AA0AC-16B2-4A62-9DFB-3966AF3E3B15-low.gifFigure 6-1 DBV Package6-Pin SOT-23Top View
GUID-DB967551-C56D-4475-BBCF-6929F7B38CA9-low.gifFigure 6-2 DRV Package6-Pin (2.00 mm × 2.00 mm) WSON With Thermal PadTop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME SOT-23 WSON
CT 4 3 I Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open results in fixed delay times (see GUID-ADD823FC-D346-4765-B603-D10601000178.html#GUID-ADD823FC-D346-4765-B603-D10601000178). Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See GUID-2B1E95D0-D594-4C7C-93D0-A21F4F0710BB.html#GUID-2B1E95D0-D594-4C7C-93D0-A21F4F0710BB for more information.
GND 2 5 — Ground
MR 3 4 I Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to VDD by a 90-kΩ pull-up resistor.
RESET 1 6 O RESET is an open-drain output that is driven to a low-impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD.
SENSE 5 2 I This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted.
VDD 6 1 I Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin.
Thermal Pad — Pad — Thermal Pad. Connect to ground plane to enhance thermal performance of package.