SBVS050N May   2004  – August 2026 TPS3808

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 SENSE Input
      2. 7.3.2 Selecting the RESET Delay Time
      3. 7.3.3 Manual RESET (MR) Input
      4. 7.3.4 RESET Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Immunity to SENSE Pin Voltage Transients
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TPS3808 DBV Package6-Pin SOT-23Top ViewFigure 5-1 DBV Package6-Pin SOT-23Top View
TPS3808 DRV Package6-Pin (2.00mm × 2.00mm) WSON With Thermal PadTop ViewFigure 5-2 DRV Package6-Pin (2.00mm × 2.00mm) WSON With Thermal PadTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME SOT-23 WSON
CT 4 3 I Reset period programming pin. Connecting this pin to VDD through a 40kΩ to 200kΩ resistor or leaving it open results in fixed delay times (see Section 6.5). Connecting this pin to a ground referenced capacitor ≥ 100pF gives a user-programmable delay time. See Section 7.3.2 for more information.
GND 2 5 — Ground
MR 3 4 I Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pull-up resistor.
RESET 1 6 O RESET is an open-drain output that is driven to a low-impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up resistor from 10kΩ to 1MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD.
SENSE 5 2 I This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted.
VDD 6 1 I Supply voltage. It is good analog design practice to place a 0.1μF ceramic capacitor close to this pin.
Thermal Pad — Pad — Thermal Pad. Connect to ground plane to enhance thermal performance of package.
(1) I = input, O = output