SGLS143E December 2002 – March 2025 TPS3820-Q1 , TPS3823-Q1 , TPS3824-Q1 , TPS3825-Q1 , TPS3828-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
| PIN | I/O | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | TPS3820‑xx‑Q1, TPS3823‑xx‑Q1, TPS3828‑xx‑Q1 | TPS3824‑xx‑Q1 | TPS3825‑xx‑Q1 | ||
| GND | 2 | 2 | 2 | — | Ground connection |
| MR | 3 | — | 4 | I | Manual-reset input. Pull low to force a reset. RESET remains low as long as MR is low and for the time-out period after MR goes high. Leave unconnected or connect to VDD when unused. |
| RESET | — | 3 | 3 | O | Active-high reset output. Either push-pull or open-drain output stage. |
| RESET | 1 | 1 | 1 | O | Active-low reset output. Either push-pull or open-drain output stage. |
| VDD | 5 | 5 | 5 | I | Supply voltage. Powers the device and monitors the voltage. |
| WDI | 4 | 4 | — | I | Watchdog timer input. If WDI remains high or low longer than the time-out period, then reset is triggered. The timer clears when reset is asserted or when WDI sees a falling edge. If left floating, the device generates pulses internally to prevent watchdog reset event. WDI must be driven low or high for watchdog error to assert output. |