SGLS143E December   2002  – March 2025 TPS3820-Q1 , TPS3823-Q1 , TPS3824-Q1 , TPS3825-Q1 , TPS3828-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Manual Reset ( MR)
      2. 7.3.2 Active High or Active Low Output
      3. 7.3.3 Push-Pull or Open-Drain Output
      4. 7.3.4 Watchdog Timer (WDI)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Supply Rail Monitoring with Watchdog Time-out and 200ms Delay
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Decoupling WDI During Reset Event
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
        1. 9.1.1.1 Related Links
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VOH High-level output voltage RESET TPS382x-25-Q1 VDD = VIT– + 0.2V, IOH = –20µA 0.8 × VDD V
TPS382x-30-Q1 VDD = VIT– + 0.2V, IOH = –30µA
TPS382x-33-Q1
TPS382x-50-Q1 VDD = VIT– + 0.2V, IOH = –120µA VDD – 1.5V
RESET TPS3824-25-Q1
TPS3825-25-Q1		 VDD ≥ 1.8V, IOH = –100µA 0.8 × VDD
TPS3824-30-Q1
TPS3825-30-Q1		 VDD ≥ 1.8V, IOH = –150µA
TPS3824-33-Q1
TPS3825-33-Q1
TPS3824-50-Q1
TPS3825-50-Q1
VOL Low-level output voltage RESET TPS3824-25-Q1
TPS3825-25-Q1		 VDD = VIT– + 0.2V, IOL = 1mA 0.4 V
TPS3824-30-Q1
TPS3825-30-Q1		 VDD = VIT– + 0.2V, IOL = 1.2mA
TPS3824-33-Q1
TPS3825-33-Q1
TPS3824-50-Q1
TPS3825-50-Q1		 VDD = VIT– + 0.2V, IOL = 3mA
RESET TPS382x-25-Q1 VDD = VIT– – 0.2V, IOL = 1mA 0.45
TPS382x-30-Q1 VDD = VIT– – 0.2V, IOL = 1.2mA
TPS382x-33-Q1
TPS382x-50-Q1 VDD = VIT– – 0.2V, IOL = 3mA
VPOR Power-up reset voltage (1) VOL(max) = 0.4V, IOL(Sink) = 20µA 0.9 V
VIT– Negative-going input threshold voltage (2) TPS382x-25-Q1 TA = 0℃ to 85℃ 2.21 2.25 2.3 V
TPS382x-30-Q1 2.59 2.63 2.69
TPS382x-33-Q1 2.88 2.93 3
TPS382x-50-Q1 4.49 4.55 4.64
TPS382x-25-Q1 TA = –40℃ to 125℃ 2.19 2.25 2.3
TPS382x-30-Q1 2.55 2.63 2.69
TPS382x-33-Q1 2.84 2.93 3
TPS382x-50-Q1 4.44 4.55 4.64
VHYS Hysteresis at VDD input TPS382x-25-Q1 30 mV
TPS382x-30-Q1
TPS382x-33-Q1
TPS382x-50-Q1 50
IIH(AV) Average high-level input current WDI WDI = VDD, time average (DC = 88%) 120 µA
IIL(AV) Average low-level input current WDI = 0.3V, VDD = 5.5V, time average (DC = 12%) –15
IIH High-level input current WDI WDI = VDD 140 190 µA
MR MR = 0.7 × VDD, VDD = 5.5V –40 –60
IIL Low-level input current WDI WDI = 0.3V, VDD = 5.5V 140 190 µA
MR MR = 0.3V, VDD = 5.5V –110 –160
IOS Output short-circuit current (3) RESET TPS382x-25-Q1 VDD = VIT–,max + 0.2V, VO = 0V –400 µA
TPS382x-30-Q1
TPS382x-33-Q1
TPS382x-50-Q1 –800
IDD Supply current WDI, MR and outputs unconnected 15 25 µA
RMR Internal pullup resistor at MR 90 kΩ
Ci Input capacitance at MR, WDI VI = 0V to 5.5V 5 pF
(1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15µs/V.
(2) To make sure best stability of the threshold voltage, place a bypass capacitor (ceramic, 0.1μF) near the supply terminal.
(3) The RESET short-circuit current is the maximum pullup current when RESET is driven low by a microprocessor bidirectional reset pin.