SNVSCH9 April   2025 TPS388C0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
      1. 7.3.1 TPS388C0x-Q1 Power ON
      2. 7.3.2 Built-In Self Test and Configuration Load
        1. 7.3.2.1 Notes on BIST Execution
      3. 7.3.3 General Monitoring
        1. 7.3.3.1 ACTIVE Monitoring
    4. 7.4 Feature Description
      1. 7.4.1 VDD
      2. 7.4.2 Maskable Interrupt (AMSK)
      3. 7.4.3 MON
      4. 7.4.4 NRST
      5. 7.4.5 NIRQ
      6. 7.4.6 I2C
      7. 7.4.7 Packet Error Checking (PEC)
      8. 7.4.8 Window Watchdog
      9. 7.4.9 Window Watchdog Timer
    5. 7.5 Register Maps
      1. 7.5.1 Registers Overview
        1. 7.5.1.1 BANK0 Registers
        2. 7.5.1.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Automotive Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Built-In Self Test and Configuration Load

Built-In Self Test (BIST) is performed:

  1. At Power On Reset (POR), if TEST_CFG.AT_POR=1

Configuration load from OTP is assisted by ECC (supporting SEC-DED). This is to protect against data integrity issues and to maximize system availability.

During BIST, NIRQ is de-asserted (asserted in case of failure), input pins are ignored, and the I2C block is inactive with SDA and SCL de-asserted. The BIST includes device testing to meet the Technical Safety Requirements. Once BIST is completed without failure, I2C is immediately active and the device enters the IDL sate after loading the configuration data from OTP. If BIST fails and/or ECC reports Double-Error Detection (DED), NIRQ is asserted, the device enters FAILSAFE state, and a best effort attempt is made to active I2C. TEST_INFO register can provide additional information on the test results.

The detailed behavior upon success/failure of the BIST is controlled by INT_TEST and IEN_TEST registers. Reporting of the BIST results is carried out through:

  • NIRQ pin: pulled low depending on the test result and BIST_C and BIST bits in IEN_TEST
  • I_BIST_C and BIST bits in INT_TEST register depending on IEN_TEST settings
  • VMON_STAT.ST_BIST_C register bit
  • TEST_INFO[3:0] register bits